JPS5840414Y2 - Initial set pulse generation circuit - Google Patents
Initial set pulse generation circuitInfo
- Publication number
- JPS5840414Y2 JPS5840414Y2 JP3141977U JP3141977U JPS5840414Y2 JP S5840414 Y2 JPS5840414 Y2 JP S5840414Y2 JP 3141977 U JP3141977 U JP 3141977U JP 3141977 U JP3141977 U JP 3141977U JP S5840414 Y2 JPS5840414 Y2 JP S5840414Y2
- Authority
- JP
- Japan
- Prior art keywords
- initial set
- set pulse
- voltage
- diode
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Electronic Switches (AREA)
Description
【考案の詳細な説明】
本考案は、ディジタル回路の初期セットパルスを確実に
発生させる回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that reliably generates an initial set pulse for a digital circuit.
一般に制御系において例えば電動機の駆動制御回路とし
てフリップフロップ回路等で構成されるディジタル回路
を使用する場合がしばしばある。Generally, in a control system, a digital circuit composed of a flip-flop circuit or the like is often used, for example, as a drive control circuit for an electric motor.
この場合ディジタル回路の電源投入時又は電源再投入時
に電動機の駆動制御回路が確実に初期セット状態になる
ように駆動制御回路の動作停止端子に相御パルスを印加
する必要がある。In this case, it is necessary to apply a phase control pulse to the operation stop terminal of the drive control circuit to ensure that the drive control circuit of the motor is in the initial set state when the power to the digital circuit is turned on or turned on again.
例えば第１図に示す従来の回路において電源を投入し端
子ｉＫ電源電圧を印加するｔコンデンサＣ０が抵抗Ｒ１
を経て充電されトランジスタＴｒのベース電圧が増大す
る。For example, in the conventional circuit shown in FIG.
The base voltage of the transistor Tr is increased through charging.
これがためトランジスタＴｒは導通を開始し、出力端子
Ｏの出力電圧が上昇し始める。Therefore, the transistor Tr starts to conduct, and the output voltage at the output terminal O starts to rise.
この場合ａ点における電源電圧とｂ点における出力電圧
とは第２図に示す曲線Ａ及びＢに応じて上昇する。In this case, the power supply voltage at point a and the output voltage at point b increase according to curves A and B shown in FIG.
第２図においてＶ。を電動機駆動制御回路の動作電圧と
すると電源電圧（曲線Ａ）は時間ｔ。V in FIG. When is the operating voltage of the motor drive control circuit, the power supply voltage (curve A) is at time t.
で動作電圧Ｖ。に到達するが出力電圧（曲線Ｂ）はＲＣ
時定数のため遅延し時間ｔ□で動作電圧Ｖ。The operating voltage is V. but the output voltage (curve B) is RC
Due to the time constant, the operating voltage V is delayed at time t□.
に到達する。従って時間ｔ□−ｔ１の間に初期セットパ
ルスを確実に発生させることができる。reach. Therefore, the initial set pulse can be reliably generated during the time t□-t1.
しかし、電源を投入して電源電圧が電動機駆動制御回路
の動作電圧ｖｏよりも充分高くなった後に電源を一旦遮
断し電源電圧が上記動作電圧Ｖ。However, after the power is turned on and the power supply voltage becomes sufficiently higher than the operating voltage vo of the motor drive control circuit, the power is once shut off and the power supply voltage becomes the operating voltage V.
以下に降下する前に電源を再投入すると、この再投入時
の出力電圧はすでに動作電圧Ｖ。If the power is turned on again before the voltage drops below, the output voltage when turned on again is already the operating voltage V.
よりも高いため初期セットパルスを発生させることがで
きなくなる。Since it is higher than that, it becomes impossible to generate an initial set pulse.
本考案の目的はディジタル回路等において電源投入時又
は電源の一時遮断後の再投入時に初期セットパルスを確
実に発生させるように適切に接続配置した上述した種類
の初期セットパルス発生回路を提供せんとするにある。The purpose of the present invention is to provide an initial set pulse generating circuit of the type described above, which is appropriately connected and arranged so as to reliably generate an initial set pulse when power is turned on or when the power is turned on again after being temporarily cut off in a digital circuit. There is something to do.
本考案は直列接続の放電用ダイオード及び充放電コンデ
ンサと、直列接続の抵抗、ツェナーダイオード及び発光
素子との並列接続回路を電源正端子及び接地点間に設け
、前記放電用ダイオード及び充放電コンデンサの接続点
と前記抵抗及びツェナーダイオードの接続点とを相互接
続し、ほかに前記発光素子と相俟ってフォトカプラを構
成するフオ））ランジスタ及び出力抵抗の直列接続回路
を他の電圧源と接地点との間に設け、前記フォトカプラ
の動作電圧レベルをツェナーダイオードにより高めで初
期セットパルスを確実に発生させるようにしたことを特
徴とする。The present invention provides a parallel connection circuit consisting of a series-connected discharging diode and a charging/discharging capacitor, a series-connected resistor, a Zener diode, and a light emitting element between a power supply positive terminal and a ground point. The connection point and the connection point of the resistor and Zener diode are interconnected, and the series connection circuit of the transistor and the output resistor that together with the light emitting element constitutes a photocoupler is connected to another voltage source. The photocoupler is provided between the photocoupler and the photocoupler at a higher operating voltage level using a Zener diode to ensure generation of an initial set pulse.
図面につき本考案を説明する。The invention will be explained with reference to the drawings.
第３図に示すように本考案初期セットパルス発生回路で
は電源正端子１とＧＮＤとの間に放電用ダイオードＤ□
及びコンデンサＣ１を直列に接続し、ダイオードＤ１に
並列に充放電抵抗Ｒ１を接続し、且つコンデンサＣ１に
並列にツェナーダイオードＺＤ及び発光ダイオードＬＥ
Ｄの直列回路を接続する。As shown in Fig. 3, in the initial set pulse generation circuit of the present invention, a discharge diode D□ is connected between the power supply positive terminal 1 and GND.
and a capacitor C1 are connected in series, a charging/discharging resistor R1 is connected in parallel to the diode D1, and a Zener diode ZD and a light emitting diode LE are connected in parallel to the capacitor C1.
Connect the series circuit of D.
ツェナーダイオードＺＤは第４図に示す電圧−電流特性
を有するものとする。It is assumed that the Zener diode ZD has the voltage-current characteristics shown in FIG.
又、正電圧源（例えば＋５Ｖ）とＧＮＤとの間にフォト
トランジスタＰＴｒ及び出力抵抗Ｒ２を直列に接続し、
フォトトランジスタＰＴｒのエミッタと抵抗Ｒ２との接
続点から出力を取出すようにする。Further, a phototransistor PTr and an output resistor R2 are connected in series between a positive voltage source (for example, +5V) and GND,
The output is taken out from the connection point between the emitter of the phototransistor PTr and the resistor R2.
本考案によれば発光ダイオードＬＥＤとフォトトランジ
スタＰＴｒとをもってフォトカプラＰＣを構成する。According to the present invention, a photocoupler PC is constituted by a light emitting diode LED and a phototransistor PTr.
斯様に構成した本考案初期セットパルス発生回路におい
て、フォトカプラＰＣは３点の電圧が電動機駆動制御回
路の動作電圧７０以上になると動作を開始するものとす
る。In the initial set pulse generation circuit of the present invention configured in this manner, the photocoupler PC starts operating when the voltages at three points reach the operating voltage of the motor drive control circuit of 70 or higher.
今、電源が投入されると点ｄの電圧は第５図の曲線ＣＫ
−沿って増大し時間ｔｏで駆動制御回路の動作電圧７０
以上となり時間ｔｌ′でツェナー電圧ｖ１以上となりそ
の後はぼ飽和値となる。Now, when the power is turned on, the voltage at point d is the curve CK in Figure 5.
- the operating voltage of the drive control circuit increases along with time to 70
As a result, the Zener voltage exceeds v1 at time tl', and thereafter reaches almost the saturation value.
この場合Ｃ点の電圧従ってｅ点の電圧は抵抗Ｒ１及びコ
ンデンサＣ□の時定数に応じて曲線ＤＫ沿い増大し時間
ｔ１で駆動制御回路の動作電圧Ｖ。In this case, the voltage at point C, and therefore the voltage at point e, increases along curve DK in accordance with the time constant of resistor R1 and capacitor C□, and at time t1 reaches the operating voltage V of the drive control circuit.
以上となり且つ時間ｔ２でツェナー電圧Ｖ＋以上となり
その後はぼ飽和値に到達する。At the time t2, the Zener voltage becomes equal to or higher than the Zener voltage V+, and thereafter almost reaches the saturation value.
これがため第３図に示す回路の出力端子ＯＫは時間ｔ２
で初期セットパルスが発生し得るようになる。Therefore, the output terminal OK of the circuit shown in FIG.
The initial set pulse can now be generated.
即ち、時間ｔ□′でツェナーダイオードＺＤが導通を開
始し、発光ダイオードＬＥＤが発光を開始し、これによ
りフォトトランジスタＰＴｒが励起されそのコレクター
エ□ツタ回路に電流が流れ始めるようになり時間ｔ２で
出力パルスを発生するようになる。That is, at time t□', the Zener diode ZD starts conducting, the light emitting diode LED starts emitting light, this excites the phototransistor PTr, and current begins to flow through its collector electrode circuit, and at time t2. It begins to generate output pulses.
次いで時間ｔ３で電源を遮断すると電源電圧は降下し始
めるがこの電圧が駆動回路の動作電圧ｖ。Next, when the power supply is cut off at time t3, the power supply voltage begins to drop, and this voltage becomes the operating voltage v of the drive circuit.
以下に降下する前に時間ｔ３′で電源を再投入するとこ
の再投入時の電源電圧は上記動作電圧ｖｏよりも大きい
がツェナー電圧ｖ０よりも小さいためツェナーダイオー
ドＺＤは非導通状態にあり従って発光ダイオードＬＥＤ
は発光せずフォトトランジスタＰＴｒも非導通状態を保
持し出力パルスは発生しない。If the power is turned on again at time t3' before the voltage drops to LED
does not emit light, the phototransistor PTr also remains non-conductive, and no output pulse is generated.
電源電圧が更に増大して時間ｔ３″で再びツェナー電圧
Ｖ□以上になるとツェナーダイオードＺＤは導通し、発
光ダイオードＬＥＤも発光し、従ってフォトトランジス
タＰＴｒのベースを励起し、このトランジスタＰＴｒを
導通し始める。When the power supply voltage increases further and becomes equal to or higher than the Zener voltage V□ again at time t3'', the Zener diode ZD becomes conductive and the light emitting diode LED also emits light, thus exciting the base of the phototransistor PTr and starting to conduct this transistor PTr. .
これがため時間ｔ４で再び初期セットパルスを確実に発
生するようになる。This ensures that the initial set pulse is generated again at time t4.
換言すれば従来の回路における時間ｔ。In other words, the time t in the conventional circuit.
−４０が本考案の時間ｔ１′〜ｔ２及び時間ｔ３”〜ｔ
４に相当するため駆動制御回路の動作電圧Ｖ。-40 is the time t1'~t2 and the time t3''~t of the present invention.
4, which is the operating voltage V of the drive control circuit.
よりも高い電圧範囲で電源をオン・オフさせても充分確
実にパルスを発生させることができる。Pulses can be generated reliably even when the power is turned on and off in a higher voltage range.
上述した所から明らかなように本考案によればツェナー
ダイオードＺＤとフォトカプラＰＣとを組合せて使用し
、ツェナーダイオードＺＤＫよりフォトカプラＰＣのバ
イアス電圧を高い値に保持することにより初期セットパ
ルスを確実に発生させることができる。As is clear from the above, according to the present invention, the Zener diode ZD and the photocoupler PC are used in combination, and the bias voltage of the photocoupler PC is maintained at a higher value than that of the Zener diode ZDK, thereby ensuring the initial set pulse. can be generated.
第１図は従来の初期セットパルス発生回路を示す構成配
置図、第２図は同じくその動作説明用波形図、第３図は
本考案初期セットパルス発生回路の構成を示す接続配置
図、第４図はツェナーダイオードの電圧−電流特性を示
す波形図、第５図は本考案初期セットパルス発生回路の
動作説明用波形図である。
Ｒ１・・・・・・充放電抵抗、Ｃ□・・・・・・コンデ
ンサ、Ｄ□・・・・・・ダイオード、ＺＤ・・・・・・
ツェナーダイオード、ＬＥＤ・・・・・・発光ダイオー
ド、ＰＴｒ・・・・・・フォトトランジスタｘＲ２・・
・・・・出力抵抗、ＰＣ・・・・・・フォトカプラ。FIG. 1 is a configuration diagram showing a conventional initial set pulse generation circuit, FIG. 2 is a waveform diagram for explaining its operation, FIG. 3 is a connection layout diagram showing the configuration of the initial set pulse generation circuit of the present invention, and FIG. The figure is a waveform diagram showing the voltage-current characteristics of a Zener diode, and FIG. 5 is a waveform diagram for explaining the operation of the initial set pulse generating circuit of the present invention. R1...Charge/discharge resistor, C□...Capacitor, D□...Diode, ZD...
Zener diode, LED...Light emitting diode, PTr...Phototransistor xR2...
...Output resistance, PC...Photocoupler.
Claims (1)
直列接続の抵抗、ツェナーダイオード及び発光素子との
並列接続回路を電源正端子及び接地点間に設け、前記放
電用ダイオード及び充放電コンデンサの接続点と前記抵
抗及びツェナーダイオードの接続点とを相互接続し、ほ
かに前記発光素子と相俟ってフォトカプラを構成するフ
ォトトランジスタ及び出力抵抗の直列接続回路を他の電
圧源と接地点との間に設け、前記フォトカプラの動作電
圧レベルをツェナーダイオードにより高めて初期セット
パルスを確実に発生させるようにしたことを特徴とする
初期セットパルス発生回路。A discharging diode and a charging/discharging capacitor connected in series,
A parallel connection circuit with a series-connected resistor, a Zener diode, and a light emitting element is provided between a power supply positive terminal and a ground point, and a connection point of the discharge diode and charge/discharge capacitor and a connection point of the resistor and Zener diode are interconnected. In addition, a series connection circuit of a phototransistor and an output resistor which together with the light emitting element constitute a photocoupler is provided between another voltage source and a ground point, and the operating voltage level of the photocoupler is set to a Zener diode. An initial set pulse generation circuit characterized in that the initial set pulse is generated reliably by increasing the initial set pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3141977U JPS5840414Y2 (en) | 1977-03-17 | 1977-03-17 | Initial set pulse generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3141977U JPS5840414Y2 (en) | 1977-03-17 | 1977-03-17 | Initial set pulse generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53126520U JPS53126520U (en) | 1978-10-07 |
| JPS5840414Y2 true JPS5840414Y2 (en) | 1983-09-12 |
Family
ID=28882957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3141977U Expired JPS5840414Y2 (en) | 1977-03-17 | 1977-03-17 | Initial set pulse generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840414Y2 (en) |
-
1977
- 1977-03-17 JP JP3141977U patent/JPS5840414Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53126520U (en) | 1978-10-07 |
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