JPS5839021A - Inspection of semiconductor device - Google Patents

Inspection of semiconductor device

Info

Publication number
JPS5839021A
JPS5839021A JP56137215A JP13721581A JPS5839021A JP S5839021 A JPS5839021 A JP S5839021A JP 56137215 A JP56137215 A JP 56137215A JP 13721581 A JP13721581 A JP 13721581A JP S5839021 A JPS5839021 A JP S5839021A
Authority
JP
Japan
Prior art keywords
forward voltage
measured
semiconductor device
chamber
normal temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56137215A
Other languages
Japanese (ja)
Other versions
JPS649731B2 (en
Inventor
Yoshihide Nakamura
吉秀 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP56137215A priority Critical patent/JPS5839021A/en
Publication of JPS5839021A publication Critical patent/JPS5839021A/en
Publication of JPS649731B2 publication Critical patent/JPS649731B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7865—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To accurately detect the loose contact of the semiconductor device in a short time by a method wherein the forward voltage of the semiconductor device is measured at the normal temperature and a fixed high temperature respectively. CONSTITUTION:A thyristor which was placed on a carrier 9 is sent to a high temperature chamber 11 from a chamber of normal temperature 10. Probes 12 and 13 are provided in the chambers 10 and 11 respectively. First, the forward voltage V1 at the normal temperature is measured by the probe 12 located in the chamber of normal temperature, and the measured value is sent to a memory and arithmetic operational circuit 14 and memorized there. Then, the thyristor is heated up to a fixed high temperature in the heating chamber 11, the forward voltage is measured again using the probe 13, the measured value is sent to the memory and arithmetic operational circuit 14, the differences between V1 and V2 or between V1 and V3 are calculated at the circuit 14, the obtained value is compared with the reference voltage V0 by a comparative judging circuit 15, and if the difference is (V1-V2)>=V0, a decision is given as a non-defective article, and if the difference is (V1-V3)<=V0, a decision is given as a defective article. Through these procedures, a plurality of semiconductor devices can be reliably inspected continuously at a high speed.

Description

【発明の詳細な説明】 この発明は半導体装置のボンディングワイヤの！１＃！
不良を検出する検査方法に関する。[Detailed Description of the Invention] This invention relates to bonding wires for semiconductor devices! 1#!
This invention relates to an inspection method for detecting defects.

トツンジス！＋サイ、リスクなどの半導体装置は基板上
に４に４体ベレットをマクントシ、基板の近傍に配置し
九リードと半導体ベレットの貴般的である。このワイヤ
ボンデイノ！は超音波ボンディングや熱圧着ボンデイン
ｌなどで行われ、そのボンディング５！１度はワイヤの
破断荷嵐會糊定して行なわれるが、情Ｍ１１％−ルド等
により、外装後は実施できない、また、ワイヤの半導体
ベレットの電極中リードとの接続部の電気的接続が不十
分だと、長時間の使用時にオープン千歳となることがあ
ゐ、このようなワイヤの！Ｉ続不十分、いわゆゐルーズ
コンタクトは引張り試験などの機械的な方法で検出する
ことが困峻であゐため、現在は製造されて製品となった
半導体装置のＲＮで、順方向電圧ｔｍ測定して、七〇綱
定値でルーズコンタクトの有無を判定したシ、順方向特
性の波形をｉｉｌ＃ｊしてルーズコンタクトを見出す方
法で行っている。Totsunzisu! Semiconductor devices such as ``Sai'' and RISK are commonly used with 4 leads placed on a substrate, and 9 leads and semiconductor pellets placed near the substrate. This wire bondino! This is done by ultrasonic bonding, thermocompression bonding, etc., and the bonding is done by fixing the broken load of the wire. If the electrical connection between the wire and the lead in the electrode of the semiconductor pellet is insufficient, it may become open during long-term use. Insufficient I connection, so-called loose contacts, is difficult to detect using mechanical methods such as tensile tests. After measuring and determining the presence or absence of a loose contact using a fixed value of 70, the waveform of the forward direction characteristic is used to find a loose contact.

とζろが、半導体装置の順方向電圧は半導体ベレットの
不＃Ｉ愉拡款状態のバラツキ等の影響で個々の製品によ
ってバラツキがあり、この順方向電圧の綱定値からルー
ズコンタクトを正確に判定することが難しかった・また
、波形ａｍ−目ａＫｓらねばならず、高稽度の検出が可
能でも、檎査工１１ｔが多くて作業性が悪かった・本発
明はかかる現状に鑑み、半導体装置のルーズコンタク）
ｌ短時間で、面も尚種度に検出する方法を提供する・以
下本発明の方法を例えばサイリスタを例にとって説明す
る。However, the forward voltage of a semiconductor device varies depending on the individual product due to the influence of variations in the condition of the semiconductor bullet, etc., and loose contacts cannot be accurately determined from the standard value of this forward voltage.・Also, it was necessary to measure the waveform am-to-aKs, and even though a high degree of detection was possible, the work efficiency was poor due to the large number of inspectors. ・In view of the current situation, the present invention loose contact)
Providing a method for accurately detecting surfaces in a short time The method of the present invention will be explained below by taking a thyristor as an example.

製品化された伊イリスＩの一例を第７図に示すと％＋１
１は放熱板、（りは放熱板１１）と一体のアノードリー
ド、（Ｓ）及び（４：は放熱板（１）の近傍に位置する
カソードリ、−ド及びゲートリード、（１１け放熱板（
１）上にマウントされたサイリスタのベレツ）、（＠１
はベレットＨｔ＋のカソード電極とカソードリード（３
）にボンディングされたワイヤ、（１）はペレットｉｌ
ｌのゲート電極とゲートリード（４）Ｋボンディングさ
れたワイヤであＪ’　ｓ　ｔｓ＋け外装ａｍ材であゐ・
い壕、このサイリス／に順方向電流”ｊｒ（）が規定値
工。七なるゲート順方向電圧ｖＦ（）　−すなわちリー
ド１ｍ＋＋４；関の電圧を調定すゐと、咎ワイヤ（組（
１１の両端の接続部がルーズコンタクトのない良品の場
合は、各ワイヤ１ｉｌｌ　（７）の接続部の抵抗が無視
で酉て、ベレツ）　！Ｉｌｌの拡散状態だけで決まる順
方向電圧”ＰＣｋが求まる・これに対して、ルーズ；ン
タクトのある不良品では、抵抗成分の電圧降下が順方向
電圧ｖＦＧに加わす、ことで順方向電圧’ＪＦＧは負の
温度係数を有す為が、抵抗成分は正の温度係ａｔ″有す
るｅ つま〉、ノつのすイリスメの各条件下でのマ、Ｇ　−Ｘ
ＩＣｋ４１性をｌＢ′−図のグラフで説明すると、ルー
ズ；ンメタトの良品及び不良品に対する常温關定時にお
ける規定電流工。（対するマＦＧがマ、になるとした゛
場合、このすイリスタを一定の高温下で再度マ１ａを肯
定すると定電流工。に対して良品の場合はマ、　（Ｖｊ
Ｉ（マ、）Ｋ、不良品の場合はマ！Ｓ（”Ｒ＜”＆＜マ
λ）Ｋなる。この不良品のｖ３はルーズ：１ｙメＩトの
あり部分での抵抗が温度上昇によって増加し、この起電
力が本来の順方向電圧マ３にＳ加され九結果の値である
。このようにして肯定された各順方向電圧Ｖλ、マ訃ｖ
３の夫々の値はｊＩｌ＆毎に多少のバラツキがあるが、
その着であｈｖｌ−マ罵の鎖中マ１−ｖ３の値は製品間
においてほぼ一定であることが分つた・本発明はとのＶ
、−１１４とＶ、−Ｖ８の差がほぼ一定であることを利
用した慣査方法で、例えば第３図に示す簀領で行う・翅
ち、搬送体（９−にサイリスタを滅せて常温呈ａ珈から
高温加熱３ｉ１（Ｉｌｌへと送ルａ一方、コノ各＊　〕
ＭＬ　（ＩＩ（ｉｌｌ　Ｋ　ｌＩ　ｆＲＬＪＢ　９ｍを
設置する。そして、まず常温憲叫の探針−で常温時での
順方向電圧ｖｌを測定して、その測定値を記憶・演算回
路Ｏりに送って記憶させる。次に、このサイリスタが高
温ｒｔｏｔ＋で一定の高温に加熱されると、探針Ｉで再
度順方向電圧を求めて、その測定値（Ｖ、かマ３）を記
憶演算回路（１４１に送り、ここで先の値ｖｌとの差Ｖ
ニーｖ２　或は差マ、−Ｖ。Figure 7 shows an example of the commercialized Italian Iris I.%+1
1 is a heat sink, (1 is an anode lead integral with the heat sink 11), (S) and (4 is a cathode located near the heat sink (1), - is a cathode lead and a gate lead, (11 is a heat sink (1)
1) Thyristor beretz mounted on top), (@1
is the cathode electrode and cathode lead (3) of Bellet Ht+.
), (1) is the pellet il
The gate electrode and gate lead (4) are bonded wires and the exterior is made of AM material.
In this case, the forward current ``jr() in this silis/ is the specified value.The gate forward voltage vF() - that is, the lead 1m++4;
If the connections at both ends of 11 are good with no loose contacts, the resistance at the connections at each wire 1ill (7) can be ignored and the resistance will be ignored. The forward voltage ``PCk'', which is determined only by the diffusion state of Ill, can be found. On the other hand, for defective products with loose contacts, the voltage drop of the resistance component is added to the forward voltage vFG, so the forward voltage 'JFG has a negative temperature coefficient, but the resistance component has a positive temperature coefficient at''.
To explain the ICk41 characteristics using the graph of 1B'-figure, it is the specified current flow at room temperature for loose and defective products. (Assuming that MaFG becomes Ma, then if this resistor is placed under a certain high temperature and affirms Ma1a again, it becomes a constant current machine.If it is a good product, Ma, (Vj
I(Ma,)K, if the product is defective, Ma! S("R<"&<maλ)K. V3 of this defective product is loose: the resistance at a certain part of the 1y meter increases due to temperature rise, and this electromotive force is added to the original forward voltage M3, resulting in a value of 9. Each forward voltage Vλ, which is affirmed in this way, is
Each value of 3 has some variation for each jIl&,
As a result, it was found that the value of HVL-V3 in the chain was almost constant among products.
This is a conventional method that takes advantage of the fact that the difference between , -114 and V, -V8 is almost constant.For example, it is carried out in the enclosure shown in Figure 3. From presentation a to high temperature heating 3i1 (sent to Ill on the other hand, on each side*)
Install the ML (II (ill K lI fRLJB 9m). Then, first measure the forward voltage vl at room temperature with the probe of the room temperature probe, and send the measured value to the memory/arithmetic circuit O. Next, when this thyristor is heated to a constant high temperature at high temperature rtot+, the forward voltage is determined again with the probe I, and the measured value (V, power 3) is sent to the memory calculation circuit (141). Here, the difference V from the previous value vl
Knee v2 or difference, -V.

を求めて、この差を比較判定回路Ｏ！で基準電圧ｖ０ト
比較シ、＊　（Ｔ、−Ｖ、　）≧ｖ０ならば良品と判定
し、差（Ｖニーｖ、　）　（Ｖｏ　　ならば不良品と判
定する。このようＫすれば確５ＡＫ、而も複数個を高速
で連続して検査することができる。Find this difference and use the comparison judgment circuit O! If the reference voltage v0 is compared with * (T, -V, )≧v0, it is determined to be a good product, and if the difference (V, ) (Vo is, it is determined to be a defective product. Furthermore, multiple items can be inspected continuously at high speed.

尚、本発明はサイリスタＫｌａらずに、上記特性を持つ
半導体装置ならば全てに適用できる。Note that the present invention can be applied to any semiconductor device having the above-mentioned characteristics, without using the thyristor Kla.

例えば、トランジスタの場合はベース・エミツメ順方向
電圧が常温時と高温時で上記サイリスタと同じ特性を有
するので、このベース・工（ツｌ順方向電圧の常温時と
高温時の２回の測定で実行できる・ 以上説明したように、本発明によれば順方向電圧特性Ｋ
Ｊ１１１品間のバラツキがあっても容易に且つ正確にル
ーズコンタクトの有無が検出で麺、而も検査の高速化や
自動化が可能となる。For example, in the case of a transistor, the base-to-emitter forward voltage has the same characteristics as the thyristor mentioned above at room temperature and high temperature. As explained above, according to the present invention, the forward voltage characteristic K
Even if there are variations between J111 products, the presence or absence of loose contacts can be easily and accurately detected, and inspection can be speeded up and automated.

【図面の簡単な説明】[Brief explanation of the drawing]

第７図は半導体装置の一例（サイリスタ）を示す一部断
面平面図、第、、２１！ｉｉｉは本発明の検査原理を説
明するための順方向電圧特性グラフ図、ｍＪ図は本発明
の方法ｔ−爽施する装置の一例を示す概略側［ｉ図であ
ゐ・ １１１　＠　＊基板（放熱板）　ｓ　１ｍ１１４！　１
１　＠リード、１６１−・半導体ベレット、ｍ（２１・
・ワイヤ。FIG. 7 is a partially sectional plan view showing an example of a semiconductor device (thyristor), No. 21! iii is a forward voltage characteristic graph for explaining the inspection principle of the present invention, and mJ is a schematic side showing an example of an apparatus for carrying out the method t of the present invention. Heat sink) s 1m114! 1
1 @ lead, 161-・semiconductor pellet, m(21・
・Wire.

Claims (1)

【特許請求の範囲】[Claims] １１１　　ワイヤで半導体ベレットのｔｍとリードと電
気的１１！続し九半導体装置の順方向電圧を常ｆｆ１時
と一定の高温時で夫々画定して、七の各漏定値の差でも
つ、て前記ワイヤ僧続部の良、不良會判定すゐようにし
たことｔｍ徴とする半導体装置の検査方法・111 Wire to semiconductor bullet tm, lead and electrical 11! Next, define the forward voltage of the semiconductor device at normal ff1 and at a constant high temperature, so that the difference between the leakage values in step 7 can be used to judge whether the wire connection is good or bad. Inspection method for semiconductor devices that detects tm signs
JP56137215A 1981-08-31 1981-08-31 Inspection of semiconductor device Granted JPS5839021A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56137215A JPS5839021A (en) 1981-08-31 1981-08-31 Inspection of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56137215A JPS5839021A (en) 1981-08-31 1981-08-31 Inspection of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5839021A true JPS5839021A (en) 1983-03-07
JPS649731B2 JPS649731B2 (en) 1989-02-20

Family

ID=15193473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56137215A Granted JPS5839021A (en) 1981-08-31 1981-08-31 Inspection of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5839021A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6384132A (en) * 1986-09-29 1988-04-14 Toshiba Corp Method and apparatus for inspecting wire bonding
JPH0541435A (en) * 1991-02-13 1993-02-19 Nec Corp Inspection of semiconductor device
JPH05136230A (en) * 1991-11-14 1993-06-01 Fujitsu Ltd Diagnosis circuit of burn-in device
EP3715887A1 (en) 2019-03-29 2020-09-30 Sintokogio, Ltd. Inspecting device
EP3715886A1 (en) 2019-03-29 2020-09-30 Sintokogio, Ltd. Inspecting device
EP3719835A1 (en) 2019-03-29 2020-10-07 Sintokogio, Ltd. Inspecting device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6384132A (en) * 1986-09-29 1988-04-14 Toshiba Corp Method and apparatus for inspecting wire bonding
JPH0541435A (en) * 1991-02-13 1993-02-19 Nec Corp Inspection of semiconductor device
JPH05136230A (en) * 1991-11-14 1993-06-01 Fujitsu Ltd Diagnosis circuit of burn-in device
EP3715887A1 (en) 2019-03-29 2020-09-30 Sintokogio, Ltd. Inspecting device
EP3715886A1 (en) 2019-03-29 2020-09-30 Sintokogio, Ltd. Inspecting device
EP3719835A1 (en) 2019-03-29 2020-10-07 Sintokogio, Ltd. Inspecting device
CN111830386A (en) * 2019-03-29 2020-10-27 新东工业株式会社 Inspection apparatus

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