JPS5837944A - Mounting structure for semiconductor chip - Google Patents
Mounting structure for semiconductor chipInfo
- Publication number
- JPS5837944A JPS5837944A JP56135966A JP13596681A JPS5837944A JP S5837944 A JPS5837944 A JP S5837944A JP 56135966 A JP56135966 A JP 56135966A JP 13596681 A JP13596681 A JP 13596681A JP S5837944 A JPS5837944 A JP S5837944A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- display
- hole
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体チップの実装構造に係り、特に表示素子
駆幼用回路を集積化してなろ複枚の半導体チップを配線
パターンを有する支持基板上に高密度に実装し得る構造
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mounting structure for semiconductor chips, and in particular, it is possible to integrate display element driving circuits and to mount a plurality of semiconductor chips at high density on a support substrate having a wiring pattern. It's about structure.
斤年液晶あるい扶ＥＬ発光媒体等を用いたトッドマトリ
ックス形式の平板型表示バネｙＶｃ駆蛸回路を一体化し
た４１１１ｔのものが欅々提案されている。A 4111t display device that integrates a Todd matrix type flat display spring yVc driving circuit using a liquid crystal or EL light emitting medium has been proposed extensively.
かかる（表示パネルは、例えばシリコン等からなる一Ｐ
導体基板上にマトリックス状に集積化した画素対応のＭ
ＯＳ）ランジスタからなる駆切回路と、ジ躯初回路のド
Ｖイン′１１！権に麦示電唖を付設してその上にＥ Ｌ
Ｏ） ｌ、！ＩＩき表示媒体及び汚四磁滝が横１され
、匍記躯蛸回名によって表示媒体の磁気光学的特性を肩
板的に制−するようになっている。ところが、このよう
な従来の構成′″ｒ：は也梢：ｌｊｌ路を嘔積化する乎
導体基板の大きさによって必然的に表示・１而のスケー
ルが１囲１長されることから、大聖；１面表示の賓現を
困帷にしていた。(The display panel is made of, for example, silicon, etc.)
Pixel-compatible M integrated in a matrix on a conductive substrate
OS) A cut-off circuit consisting of a transistor and a V-in '11 of the first circuit of the body! E L
O) l,! A second display medium and a rotary magnet are placed horizontally, and the magneto-optical characteristics of the display medium are controlled in a shoulder-like manner by means of the two-dimensional display medium. However, in such a conventional configuration, the scale of the display is necessarily increased by one area and one length depending on the size of the conductor substrate that makes the path cumulate. ;It was making it difficult to show guests on the front page.
そこで１述の・、曽点を解消するため、１文字単位また
は数文字中位の画素数を有する従来と同溝収の小曵模表
示用半Ｉ！ｉ体チップを複べ個準備し、かかる半導体チ
ップを配線パターンを有する支持基板上にｌ′ｆｒ要改
組合せて配Ｗｌシ、大型表示画面を構成するといった竹
え方が提°＜されている。しかしながら、かかる表示両
面構収の方法にあっては、各小曳模表示用半導俸チップ
上の表示頭載の）に縁肩邪に、少なくとも１８号や電力
の′電礪接続パッドを設けねばならないので、その部分
だけチップの面積が広くなり、また各チップ相屹間の電
画接続をワイヤボンディング等によって表示面側で行う
ことになるので、曲記半尋俸チップの実装密度を低下さ
せるばかりでなく、構成された表示両面に上記宙礒（ｙ
統都からなる非表示部分ができるために表示彩りが不揃
いとなりグツフィック浸水が行えないといった欠点があ
った。Therefore, in order to eliminate the above-mentioned zero point, we created a half-I for displaying a small model with the same groove size as the conventional one, which has a medium number of pixels for one character or several characters. A method has been proposed in which multiple i-type chips are prepared, and these semiconductor chips are assembled on a support substrate having a wiring pattern to form a large display screen. . However, in such a method of display double-sided installation, at least a No. 18 or electric power connection pad must be provided on the edge of the display head on each small display semiconductor chip. Therefore, the area of the chip increases in that area, and the electrical connection between each chip layer must be made on the display surface side by wire bonding, etc., which reduces the packaging density of the chip. Not only that, but also the above-mentioned cloth (y
There was a drawback that the display coloring was uneven due to the formation of a hidden part consisting of the central capital, making it impossible to perform gutsphic immersion.
木発１１／１は一ヒ記従来の実情に鑑みなされたもので
その目的は、小規模表示用半導体チップの電極接暁都を
、チップ面積を広くすることなくその裏面側に収り出す
ようにして、各：ｉｉ記半弾体チップ相′装ｔ間の電極
接続を支持基板の配線パターンを用いて寝曲倶ｊで接続
することＫより、牛尋俸チップのＸ袋密１ｙの向上を図
り、かつＩ達成された表示１両面ｙ−表示形系の不揃い
が生じることのない新規な半）洋体チップの実装構造を
提供することにある。Kippatsu 11/1 was created in view of the existing circumstances, and its purpose was to accommodate the electrode contact area of a semiconductor chip for small-scale display on the back side of the chip without increasing the area of the chip. By connecting the electrodes between each semi-ballistic chip phase and t using the wiring pattern of the support substrate, the X bag density of the chip can be improved. It is an object of the present invention to provide a new semi-transparent chip mounting structure which achieves the following and which does not cause irregularities in the Y-display shape system on both sides of the display.
以Ｊ図面を用いて本発明の実施例について＃細に説明す
る。Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図は本発明の実装構造に適用する半導体チップの一
実施例を＋！Ｅ４的に示す斜視図であって、ｌはシリコ
ン等からなる半１弾体基板上にマトリックス状にＩ；−
素付心のＭＯＳ）フンジスタ等を嗅偵化する。とともＶ
Ｃ必ヅに応じてシフトＶジスタのようなアドレス（す１
路も一体横戎した躯初１４ｊｌ路・〜依であり、これら
躯頓回路へ板ｌ上に絶縁−６を介して僅数の表示セＡ／
杉゛（ｋにパターン形成された表示屯１叙１２（各表示
１礪−２は前記咄槌→６に対応して配設された図示しな
い接続化を浦してそれぞれ所定の躯初回路と接続されて
いる）及び３のエレクトロルミネッセンス層の叩き表示
媒体Ｎ、さらに透明′＃セ＠４等が１に積層されている
。そしてかかる半導体チップｌＯを図示しない配置パタ
ーンを何する支持基板上に複枚個箇ぞ関に配タリ′米装
するため、４：発明では、半導体チップ１０における１
以！１ｌｌＪｌＯ］１Ｎ！！基板ｌのｔ４縁端部に設け
る表示部１Ｊ用回路の復改の電１傘僧続都５を、前記第
１図及び男２図の要部断（−ｊ図に示すように構成する
。即ち・Ａ２図に示すように、例えば表示部１ＩｙＩａ
１回路を集積化する牛尋体基椴２１０）電・鐵接続部形
成予定部位番こあらがしめ咳基板２１を貫通する所定径
の１通孔２２を設け、前記表示駆蛸用回路を形成する・
祭の熱酸化工程によって前記貫通孔２２の内面及び前記
基板２１の表裏面に酸化絶縁幌２３を形成する。そして
前記基板２１Ｅに形成された図示しない表示躯薊用回路
または選択アドレス回路からの導出電源パターン２４を
図示のように＠記１通孔２２上にま九がろＬうに被槍１
ｅ成し、しかる後、前記貫通孔２２の内面及び該孔２２
の両開口開辺部に、例えば無゛題解メッキ唐によって典
択的に金（Ａｕ ）等からなる専亀喚２５を被４形収し
て前記導出′ｔｔ極パターン２４の″題セ接続部５をか
かる導通接続孔２２′を通して、即ち換言すれば１ＩＴ
Ｉ記駆切回路基板１Ｏ）＠面側に配設した構造とする。Figure 1 shows an example of a semiconductor chip applied to the mounting structure of the present invention. E4 is a perspective view showing I;
MOS of the basic mind) It turns Funjista etc. into a detective. Tomo V
Shift V register-like addresses (S1
The circuits are also horizontally carved and have 14 circuits at the beginning of the body, and these circuits are connected to a small number of display circuits via insulators 6 on the board.
Displays 1-12 (each display 1-2 is connected to a predetermined basic circuit by connecting connections (not shown) arranged corresponding to the above-mentioned hammers →6) The electroluminescent layer (connected) and the electroluminescent layer (3) are stacked on the display medium (1), and the transparent layer (4) is stacked on the support substrate (1). In order to arrange the plurality of chips in each section, 4: In the invention, 1 in the semiconductor chip 10
Here it is! 1llJlO] 1N! ! The circuit 5 for the circuit for the display section 1J provided on the t4 edge of the substrate 1 is configured as shown in the main section (-j) of FIGS. 1 and 2. That is, as shown in Figure A2, for example, the display section 1IyIa
210) Planned part number for forming electric/steel connection part 1 hole 22 of a predetermined diameter passing through the board 21 is provided to form the display driving circuit. do·
An oxidized insulating canopy 23 is formed on the inner surface of the through hole 22 and on the front and back surfaces of the substrate 21 by a thermal oxidation process. Then, the power supply pattern 24 derived from the display body circuit or selection address circuit (not shown) formed on the substrate 21E is placed over the through hole 22 as shown in the figure.
e, and then the inner surface of the through hole 22 and the hole 22
A special plate 25, typically made of gold (Au), is placed in the open sides of both openings, for example, by means of a non-plating plate to connect the connecting portion of the derived ``tt'' pole pattern 24. 5 through such conductive connection hole 22', in other words, 1IT
The cut-out circuit board 1O) has a structure in which it is disposed on the @ side.
かくしてこのような１−Ｊｔ成の１櫃接続部５を何する
第１図の＋４」き複枚個の半４俸チップｌＯａ、 １０
ｂ・・・・・・を第３図に示すように・セ舐接を売用
配猟パターン３２が上面に配設されたセラミック等から
なるだモ
持基板３１上１４接する形で、谷牛導俸チップ１０ａ。Thus, what to do with such a 1-Jt connecting part 5 of FIG.
b... As shown in FIG. Guiding tip 10a.
１０ｂ・・・・・・の電舐奎続部５と対応する前記配線
パターン３２とを例えば導電柱ペーストあるいは代−罎
半田等の４（性接＃斉ｊ３３を用いて這え１町に接続す
る裏面接続４１戊によって、隣接配置すれば、１４１鯰
チップ間に不必幡な非表示部分が生ずる開演を解消する
ことがＦＪｔＥとなると共に夫装置暦１丈が同上する。10b . . . and the corresponding wiring pattern 32 are connected to each other using conductive pole paste or solder, etc. If they are arranged adjacently by the rear surface connection 41, it becomes FJtE to eliminate the unavoidable non-display portion between the 141 catfish chips, and the device calendar 1 length is the same as above.
以上の説明から明らかなように本発明の半導体チップの
夫装嘴面に工れは表示孝子−１用回路を集積化してなる
半導体チップの各電１４接続部をチップ裏面側に導通接
続孔を介して収り出す構成とし、かかる構成の腹数個の
前記半導体チップを支持基板上に実装するに祭しては、
前記各半導俸チップ柑ｎ間の１４ｆ峨接続あるいは半導
体チップの１喰接続部と支持基板上の外部接続端子どの
接続を支持基板上の対応する配線パターンを用いて裏面
接続することにエリ、かかる半４体チップのｔ［ｆＩ！
ｉ接続部の占有面積が低減でき、かつチップの′長袋密
度を向上することが可能となる。また実装された隣接チ
ップ間の表示間隙を僅少できるので、高品質な大型画面
表示の実現が容り化されるＦＩＪ点を何し、この種のＥ
Ｌやエレクトロクロミック等からなる表示部を用い九平
板型表示装置の＃！ｌ成に適用して唖めて有利である。As is clear from the above description, the main feature of the semiconductor chip of the present invention is to provide conductive connection holes on the back side of the chip for each of the 14 connection parts of the semiconductor chip integrated with the display circuit 1. When the semiconductor chips of this configuration are mounted on a supporting substrate,
The connection between the 14F connection between the respective semiconductor chips or the one-way connection of the semiconductor chip and the external connection terminal on the support substrate is connected to the back surface using the corresponding wiring pattern on the support substrate; t[fI! of such a half-quad chip!
The area occupied by the i-connection portion can be reduced, and the chip density can be improved. In addition, since the display gap between adjacent mounted chips can be minimized, it is possible to realize a high-quality large-screen display.What is the FIJ point?
#! of a nine-plate type display device using a display section made of L, electrochromic, etc. It is advantageous to apply it to the construction.
また半導体チップの素子Ｆｆ３収而を面にしてフェイス
ボンディング等により支持橋板ヒに配置することのでき
ない、例えば紫外線消失望メモリ回路素子等の′ズ袋に
もＩ内用＝’Ｊ醸であり、実用−ｈ ’ｆｆ ｆすであ
る。In addition, it is also suitable for internal use in cases where the semiconductor chip element Ff3 cannot be placed on the supporting bridge board by face bonding or the like, such as memory circuit elements that cannot be erased by ultraviolet rays. , Practical-h'ff f.
・朽１図は木免用に係る半導体チップの一笑施例をｌ！
Ｅ略的に示す＠視図、第２図は本発明に係る半導体チッ
プの′１輌接続部の一′に唖例を示す品分１祈而−１第
３図は本発明に係る半導体チップの′Ｘ庚時ＶＣおけろ
各チップ相互間の′、汀）場碕部の接１面溝収の−′く
嘩例を辰す憧部折面図である。
図において１は躯切Ｉ用路Ｊ〜版、２は表示電（（ｊ−
３は没示県俸軸、４は透明′Ｎ囁−１５は１礒接続部、
ｌＯは半導体チップ、２１は半導体基板、２２は貿通孔
、２２／は、亨１市接続孔、２３は唆化絶を模、２４は
毫
・厚比１育（玉パターン、２５は・年産嘴、３１はグ持
基板、３２は′乍−覗°順・、【用配礫パターン、３３
は憚′１性接着網を示す。
第１図
第２閃
第３閃・Figure 1 is a funny example of a semiconductor chip related to wood use!
E Schematically shown @ perspective view, FIG. 2 shows an example of a connecting part of a semiconductor chip according to the present invention. Part 1 - 1 FIG. 3 shows a semiconductor chip according to the present invention. This is a cross-sectional view showing an example of the friction between the VC chips and the tangential surface grooves of the VC when the VC is placed. In the figure, 1 is the body cutting I route J~ version, 2 is the display electrode ((j-
3 is the dead prefecture shaft, 4 is the transparent 'N' whisper-15 is the 1's connection part,
1O is a semiconductor chip, 21 is a semiconductor substrate, 22 is a trade hole, 22/ is a connection hole for the first city, 23 is a model of fascination, 24 is a ball pattern, 25 is an annual production The beak, 31 is the holding board, 32 is the ``gravel distribution pattern, 33
indicates an adhesive network. Figure 1, 2nd flash, 3rd flash
Claims (1)
４ｊｉ攻個の半導体チップを、＠接装置してｆｆ！、環
パターンを有する支持基板上に実装する構造において、
前記半導体チップの各電極接続部を、該噸竜の引出部直
下に設けられた導通接続孔を通してチップ婆面側に設け
、かつ対応する前記支持基板上の配線パターンに接続し
てなることを特徴とする半導体チップの実装置ＩＩ造。A 4ji offensive semiconductor chip, which is made by integrating a circuit for display device interference on a semiconductor substrate, is connected to ff! , in a structure mounted on a support substrate having a ring pattern,
Each electrode connection portion of the semiconductor chip is provided on the front side of the chip through a conduction connection hole provided directly below the lead-out portion of the semiconductor chip, and is connected to the corresponding wiring pattern on the support substrate. Construction of actual semiconductor chip equipment II.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56135966A JPS5837944A (en) | 1981-08-28 | 1981-08-28 | Mounting structure for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56135966A JPS5837944A (en) | 1981-08-28 | 1981-08-28 | Mounting structure for semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5837944A true JPS5837944A (en) | 1983-03-05 |
Family
ID=15164012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56135966A Pending JPS5837944A (en) | 1981-08-28 | 1981-08-28 | Mounting structure for semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5837944A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6667551B2 (en) | 2000-01-21 | 2003-12-23 | Seiko Epson Corporation | Semiconductor device and manufacturing thereof, including a through-hole with a wider intermediate cavity |
-
1981
- 1981-08-28 JP JP56135966A patent/JPS5837944A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6667551B2 (en) | 2000-01-21 | 2003-12-23 | Seiko Epson Corporation | Semiconductor device and manufacturing thereof, including a through-hole with a wider intermediate cavity |
| KR100425391B1 (en) * | 2000-01-21 | 2004-03-30 | 세이코 엡슨 가부시키가이샤 | Semiconductor device and method of making the same, circuit board and electronic instrument |
| US6852621B2 (en) | 2000-01-21 | 2005-02-08 | Seiko Epson Corporation | Semiconductor device and manufacturing method therefor, circuit board, and electronic equipment |
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