JPS5837742A - Digital differential analyzer - Google Patents
Digital differential analyzerInfo
- Publication number
- JPS5837742A JPS5837742A JP56134058A JP13405881A JPS5837742A JP S5837742 A JPS5837742 A JP S5837742A JP 56134058 A JP56134058 A JP 56134058A JP 13405881 A JP13405881 A JP 13405881A JP S5837742 A JPS5837742 A JP S5837742A
- Authority
- JP
- Japan
- Prior art keywords
- register
- bit
- parallel
- adder
- differential analyzer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/64—Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Feedback Control In General (AREA)
Abstract
Description
【発明の詳細な説明】 本発明はディジタル微分解析器に関する。[Detailed description of the invention] The present invention relates to a digital differential analyzer.
既知のディジタ／Ｌ／微分解析器における基本演算は積
分である。積分はｘ、ｙの２つの入力が与えられ念とき
−ｆｙｄｘ
を満足する。これは微分形を用−て
ｄｚ−ｙｄｘ
となる、ディジタ／１／微分解析器における積分器では
ｄｘ、ｄｚとして量子化を行っ念有限の徽小量△２．Δ
ＺＫついて
△ｚ −ｙ△Ｘ
の演算を行う、ディジタル微分解析器における積分器の
基本構成を第１ｒＨに示す。Ｙレジスタ１には、初期値
ｙ、ボセットされ、Ｙレジスタ増分パルスＩＰが入力線
５に入力するたびに、加算器４ａを介して、加算され、
Ｙレジスタ１の内容は。The basic operation in known digital/L/differential analyzers is integration. Integration is given two inputs, x and y, and satisfies -fydx. Using the differential form, this becomes dz-ydx.The integrator in the digital/1/differential analyzer quantizes it as dx and dz, and assumes a finite small amount △2. Δ
The basic configuration of an integrator in a digital differential analyzer that calculates Δz −yΔX with respect to ZK is shown in the first rH. The initial value y is set in the Y register 1, and is added via the adder 4a every time the Y register increment pulse IP is input to the input line 5.
The contents of Y register 1 are:
変化分△ｙにより
３’１−７１ ｒ＋△ｙ
となる、Ｙレジスタ１の出力は、ＡＮＤゲート３を介し
て加算＠ａｂの入力＠Ｂに接続される。Ｓレジスタ２の
出力は加算器４ｂの入力線９＆ｔＪＩ続される。ＡＮＤ
ゲート５０入力入力釦７算パルスＡＰが入力されるとＹ
ｌ／Ｎスタ１の内容とＳレジスタ２の内容が加算器４ｂ
を介して加算され、加算結果は接続線１０奢経由してＳ
レジスタ２＆Ｃ格納される。ｏｖｐはオーバフローパル
スでアル。The output of the Y register 1, which is 3'1-71 r+Δy due to the change Δy, is connected to the input @B of the addition @ab via the AND gate 3. The output of S register 2 is connected to input line 9&tJI of adder 4b. AND
Gate 50 input input button 7 Y when arithmetic pulse AP is input
The contents of l/N star 1 and the contents of S register 2 are added to adder 4b.
The addition result is sent to S via the connection line 10.
Stored in registers 2&C. ovp is an overflow pulse.
Ｙレジスタ１の場合は、ＡＮＤゲート３への演算パルス
ＡＰと演算パルスＡＰの入力する間釦なされる。In the case of the Y register 1, the button is pressed while the calculation pulse AP and the calculation pulse AP are input to the AND gate 3.
Ｗ！１２図にｎビット直列演算方式のディジタル微分解
析器の構成図を示す、Ｙレジスタ１％Ｓレジスタ２は各
々ｎビットであり、Ｙレジスタ１は接続線１３を介して
加算器４ｂに接続され、Ｓレジスタ２は接続！ｉ＆１４
を介して加算ｉｎｂに接続され、加算結果は接続線１５
を経白しとＳレジスタ２に格納される。加算器４ｂの出
力はキャリーフリップフロップ１２に接続され、各ビッ
トごとの加算演算にともなうキャリー信号を保持し、次
ビットの加算演算の入力として接＃！１６を介して、加
算器４ｂの入力となる。キャリーフロップフロップ１２
の出力は、ＡＮＤゲート３により、加算タイミングｔｎ
のときのキャリーをオーバフローパルスＯＶＰとして取
り出す。なお、この図疋おりてＹレジスタ１の増分回路
部分は省略して示しである。W! FIG. 12 shows a configuration diagram of a digital differential analyzer using an n-bit serial operation method. Each of the Y register 1% and the S register 2 has n bits, and the Y register 1 is connected to the adder 4b via a connecting line 13. S register 2 is connected! i&14
is connected to the addition inb through the connection line 15, and the addition result is connected to the connection line 15.
is stored in S register 2. The output of the adder 4b is connected to a carry flip-flop 12, which holds the carry signal associated with the addition operation for each bit, and connects it as an input for the addition operation of the next bit. 16, it becomes an input to the adder 4b. carry flop flop 12
The output of tn is determined by the AND gate 3 at the addition timing tn
The carry at the time is taken out as an overflow pulse OVP. Note that the increment circuit portion of the Y register 1 is omitted from this figure.
第３図に実用に共する直列演算方式のディジタル微分解
析器の構成図を示す、ＹＭレジスタ１９は（ｎｘｍ）ビ
ットで構成され、ｎビットのレジスタがｍ個直列に接続
された構成となる。ＳＭしシス１２０は（ｎｘｍ ）ビ
ットで構成され％ｎビットのｖＮスタボｍ個直列に接続
されな構成となる。τＭしシス１１？の内容とＳＭレジ
スＪ１２０の内容は加算ＪＩ４１）を介して加算され、
加算結果＃ｉＥ３ＭｖＮｘ１２ｏＫ格ＩＡすり、 ＃−
５ｙａ ｉｔオーバフローレシス＃２１に格納される
。加算はＳ、十丁、、８．＋Ｙ、、−・・と順次実行さ
れ（Ｓｉ。FIG. 3 shows a block diagram of a digital differential analyzer using a serial operation method that is used in practical use. The YM register 19 is composed of (nxm) bits, and has a configuration in which m registers of n bits are connected in series. The SM system 120 is composed of (nxm) bits, and has a configuration in which m vN stabs of n bits are connected in series. τM and Sis 11? The contents of and the contents of SM register J120 are added via addition JI41),
Addition result #iE3MvNx12oK rating IA slip, #-
5ya it is stored in overflow ratio #21. The addition is S, Jucho, 8. +Y, -... are executed sequentially (Si.
＋Ｙ１）の加算演算には（Ｓｉ−、＋Ｙｉ−，）以前Ｋ
１１１行されたオーバフローが反映される１本構成の直
列演算方式による演算時間は、１ビツトの加算に要する
時間を△を時間とするとｎビットの演算時間は
ｎ×Δｔ
となＬｍ個の積分演算に要する時間は
ｍｘｎｘΔｔ
となる、直列演算方式によるディジタル微分解析器は八
−ドウエア規模が小さ−と−う利点はあるが、演算速度
がおそ−と−う欠点をもつ、演算を高速化する手段とし
て第２図の構成から成る積分器をディジタル微分解析器
の１演算単位として。For the addition operation of +Y1), (Si-, +Yi-,) is previously K
The calculation time for a single-line serial calculation system that reflects the overflow of 111 lines is: If the time required to add one bit is △, then the calculation time for n bits is n x Δt. Lm integral calculations The time required for the calculation is mxnxΔt.A digital differential analyzer using a serial calculation method has the advantage of having a small 8-domain scale, but has the disadvantage of slow calculation speed.It is a means of speeding up calculations. Assume that the integrator with the configuration shown in Fig. 2 is one calculation unit of the digital differential analyzer.
歳
ｍ個の積分単位を構成−４列に演算を実行せしめる方法
がある。一本方式は一般に並列演算方式と呼ばれており
、演算時間は、
ｎｘΔｔ
と高速になる。しかし、並列演算方式はディジタル微分
解析器の構成要素として、ｎ（［の加算器とｎビットの
レジスタが２ｍ個必要となる。There is a method of constructing m integral units and performing calculations in -4 columns. The single-line method is generally called a parallel calculation method, and the calculation time is as fast as nxΔt. However, the parallel operation method requires n([ adders and 2m n-bit registers as components of the digital differential analyzer.
本発明の目的は、直列演算方式と並列演算方式の欠点を
補い、利点をとりいれた構成のディジタル微分解析器を
供するＫある。SUMMARY OF THE INVENTION An object of the present invention is to provide a digital differential analyzer having a configuration that compensates for the drawbacks of the serial calculation method and the parallel calculation method and incorporates the advantages.
以下、第４図に示す本発明の一実施例につ−て説明する
。本ディジタＡ／微分解析器の基本構成要素はｍビット
のレジスタｎ個から成るＹしＶスＩ群とｍビットのレジ
スタｎ個から成るＳレジスタ群とｎビット加算器とオー
バフローパルスＩから成る。な訃、増分回路部分は省略
して示しである。An embodiment of the present invention shown in FIG. 4 will be described below. The basic components of this digital A/differential analyzer are a Y/V/I group consisting of n m-bit registers, an S register group consisting of n m-bit registers, an n-bit adder, and an overflow pulse I. Unfortunately, the incremental circuit portion is omitted from the illustration.
すなわち、本発明によれば図に示す如＜ｓｍビットのレ
ジスタｎ個を並列に配置し、各レジオＩの１ビツト目を
集合しなレジスタをＹ、レジオＩ。That is, according to the present invention, as shown in the figure, n registers of <sm bits are arranged in parallel, and the first bit of each register I is set as register Y, register I.
２ビツト目を集合したしＮｘ夕をＹ、レジオＩ。I gathered the 2nd bit, Nx evening, Y, Regio I.
以下同様にしてｍビット目を集合しなレジスタをＹｍし
シスＩとなし１ｍ個のＹレジスタ群を構成すする。Thereafter, in the same manner, the m-th bit is collected and the register is designated as Ym and is designated as system I to form a group of 1m Y registers.
同様に、ｍビットのレジスタｎ個繻を並列に配置し、各
レジスタの１ビツト目を集合したレジスタをＳｌレジス
タ、２ビツト目を集合したレジスタをＳ、レジスタ、以
下同様にしてｍビット目を集ス
合し冷レジスタをＳｍレジ（りとなし、ｍ個のＳレジス
タ群を構成する。ＹＭルジスメ２２とＳＭルジスタ２５
は接続！Ｉ２９と接続線３２を介して、加算器２Ｂに接
続する。ＹＭルジスタｎの内容とＳＭルジスタ２５７）
内容は加算器２８によって加算演算１！８５ｉＩ！行さ
れ、その加算結果はＳＭｌしｙスタフ５に接続線３５を
経由して格納される。以下同様にして、ＹＭ２＋５ＩＩ
ｉ２．・・・、Ｙビ
Ｍｎ＋ＳＭｎの演算が並行して実行される。１〜ツトの
加算に要する時間をΔｔ′とすると本構成になるｎピッ
）ｍ個の積分演算に要する時間はｍ×△ｔ′
となり、直列演算に比し、演算時間は１／ｎに短縮され
る。Similarly, n m-bit registers are arranged in parallel, and the register that collects the first bit of each register is the Sl register, the register that collects the second bit is the S register, and so on. The cold registers are grouped together to form a group of m S registers. YM Lujisume 22 and SM Lujistor 25
is connected! It is connected to the adder 2B via I29 and the connection line 32. Contents of YM Lujista n and SM Lujista 257)
The content is an addition operation 1!85iI! by the adder 28. The addition result is stored in the SM1 y stuff 5 via the connection line 35. Similarly, YM2+5II
i2. ..., YbiMn+SMn calculations are executed in parallel. If the time required to add 1 to t is Δt', the time required to perform n-pi) m integral operations in this configuration is m x △t', and compared to serial calculation, the calculation time is reduced to 1/n. be done.
以上説明した如く、本発明によれば、直列演算方式と並
列演算方式の各々の欠点をなくし、それらの利点を奮す
る高速、安価なディジタル微分解析器を得ることができ
る。As described above, according to the present invention, it is possible to obtain a high-speed, inexpensive digital differential analyzer that eliminates the drawbacks of the serial calculation method and the parallel calculation method and takes advantage of their advantages.
１１１図は、ディジタル微分解析器を説明するためのブ
ロック結線図、菖２図は従来のｎビット直列演算方式の
ディジタル微分解析器を示すブロック結線図、第３図は
従来のｍ個の積分要素をもつ直列演算方式のディジタル
微分解析器を示すブロック結線図、第４図は本発明の直
並列ディジタル微分解析器の一冥施例を示すブロック結
線図である。
２２．２３．２４：Ｙレジスタ群、２５，２６゜２７＋
Ｓレジスタ群、２８：ｎビットの加算器。
代理人 弁理士 薄 １） 利 幸臂１図
Ｐ
第２図
第３図
第４口Fig. 111 is a block wiring diagram for explaining a digital differential analyzer, Fig. 2 is a block wiring diagram showing a conventional n-bit serial calculation type digital differential analyzer, and Fig. 3 is a conventional block wiring diagram for explaining a digital differential analyzer with m integral elements. FIG. 4 is a block diagram showing one embodiment of the serial-parallel digital differential analyzer of the present invention. 22.23.24: Y register group, 25, 26° 27+
S register group, 28: n-bit adder. Agent Patent Attorney Susuki 1) Yukio Tori 1 Figure P Figure 2 Figure 3 Figure 4 Entrance
Claims (1)
成したｍビットのレジスタをｎ個並列に配置して成るＹ
レジスタ群と、対応する各ビ・ソトを各々集合して構成
したｍビットのレジスゲをｎ個並列にｆｇ！置して成る
Ｓレジスタ群とを具備し。 加Ｘ演算をなすことを特徴とするディジタル微分解析器
。[Claims] Y consisting of n m-bit registers arranged in parallel, each consisting of an n-bit adder and a set of corresponding bits.
fg! n m-bit registers, each consisting of a group of registers and a set of corresponding bis and sotos, are arranged in parallel. and a group of S registers. A digital differential analyzer characterized by performing an additive X operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56134058A JPS5837742A (en) | 1981-08-28 | 1981-08-28 | Digital differential analyzer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56134058A JPS5837742A (en) | 1981-08-28 | 1981-08-28 | Digital differential analyzer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5837742A true JPS5837742A (en) | 1983-03-05 |
| JPS6138494B2 JPS6138494B2 (en) | 1986-08-29 |
Family
ID=15119376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56134058A Granted JPS5837742A (en) | 1981-08-28 | 1981-08-28 | Digital differential analyzer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5837742A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4830423A (en) * | 1986-10-27 | 1989-05-16 | Honda Giken Kogyo Kabushiki Kaisha | Adjustable windshield for vehicle |
-
1981
- 1981-08-28 JP JP56134058A patent/JPS5837742A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4830423A (en) * | 1986-10-27 | 1989-05-16 | Honda Giken Kogyo Kabushiki Kaisha | Adjustable windshield for vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6138494B2 (en) | 1986-08-29 |
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