JPS5832527U - reset circuit - Google Patents

reset circuit

Info

Publication number
JPS5832527U
JPS5832527U JP12520681U JP12520681U JPS5832527U JP S5832527 U JPS5832527 U JP S5832527U JP 12520681 U JP12520681 U JP 12520681U JP 12520681 U JP12520681 U JP 12520681U JP S5832527 U JPS5832527 U JP S5832527U
Authority
JP
Japan
Prior art keywords
reset circuit
parallel circuit
circuit
sanode
zener
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12520681U
Other languages
Japanese (ja)
Inventor
亀本 一廣
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP12520681U priority Critical patent/JPS5832527U/en
Publication of JPS5832527U publication Critical patent/JPS5832527U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のリセット回路を示す回路図、第2図は第
1図の各部の波形を示す動作説明用の波形図、第3図は
本考案の実施例を示す回路図、第4図は第3図の各部の
波形を示す動作説明用の波形図である。 21・・・入力端、23.29・・・出力端、25・・
・トランジスタ、26・・・抵抗、27・・・コンデン
サ、28・・・ツェナーダイオード。
Fig. 1 is a circuit diagram showing a conventional reset circuit, Fig. 2 is a waveform diagram for explaining operation showing waveforms of each part in Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the present invention, Fig. 4 3 is a waveform diagram for explaining the operation, showing waveforms of each part in FIG. 3. FIG. 21...Input end, 23.29...Output end, 25...
・Transistor, 26...Resistor, 27...Capacitor, 28...Zener diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ベースが基準電圧に保持されることにより入力される非
安定化入力電圧を安定化して出力する直列制御用トラン
ジスタと、前記段−スとカソード接地のツェナーダイオ
ードのサノードとの間に挿入した抵抗及びコンデンサの
並列回路及びこの並列回路にツェナー電流検出用トラン
ジスタとを具備することを特徴とするリセット回路。
A series control transistor whose base is held at a reference voltage to stabilize and output an unregulated input voltage, and a resistor inserted between the stage and the sanode of the Zener diode whose cathode is grounded. A reset circuit comprising a parallel circuit of capacitors and a Zener current detection transistor in the parallel circuit.
JP12520681U 1981-08-26 1981-08-26 reset circuit Pending JPS5832527U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12520681U JPS5832527U (en) 1981-08-26 1981-08-26 reset circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12520681U JPS5832527U (en) 1981-08-26 1981-08-26 reset circuit

Publications (1)

Publication Number Publication Date
JPS5832527U true JPS5832527U (en) 1983-03-03

Family

ID=29919051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12520681U Pending JPS5832527U (en) 1981-08-26 1981-08-26 reset circuit

Country Status (1)

Country Link
JP (1) JPS5832527U (en)

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