JPS5824838U - reset circuit - Google Patents

reset circuit

Info

Publication number
JPS5824838U
JPS5824838U JP11908781U JP11908781U JPS5824838U JP S5824838 U JPS5824838 U JP S5824838U JP 11908781 U JP11908781 U JP 11908781U JP 11908781 U JP11908781 U JP 11908781U JP S5824838 U JPS5824838 U JP S5824838U
Authority
JP
Japan
Prior art keywords
reset circuit
power supply
voltage
capacitor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11908781U
Other languages
Japanese (ja)
Inventor
歓崎　実
邦彦 井上
Original Assignee
日本電信電話株式会社
松下電送株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電信電話株式会社, 松下電送株式会社 filed Critical 日本電信電話株式会社
Priority to JP11908781U priority Critical patent/JPS5824838U/en
Publication of JPS5824838U publication Critical patent/JPS5824838U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のリセット回路を示す回路図、第２図は前
記従来のリセット回路における電圧波形図、第３図は本
−案によるリセット回路の一実施例を示す回路図、第４
図は本考案の他の実施例を示す回路図、第５図は前記各
実施例における電圧波形図である。 ｃ、、　Ｃ１，７ｍｍ　ｍｍｍ　：７ンデンサ、Ｑａｌ
　＠　Ｑ’ａ２１　Ｑ　ｂｌ　＊　　Ｑｂ２・・・・・
・トランジスタ、Ｒ，１〜Ｒａ４．　Ｒ，□〜Ｒｂ４・
・・・・・抵抗、ｖＣＣ・・・・・・電源電圧、Ｓ、、
　Ｓｂ・・・・・・リセット信号。 第２図。 第５図FIG. 1 is a circuit diagram showing a conventional reset circuit, FIG. 2 is a voltage waveform diagram in the conventional reset circuit, FIG. 3 is a circuit diagram showing an embodiment of the reset circuit according to the present invention, and FIG.
The figure is a circuit diagram showing another embodiment of the present invention, and FIG. 5 is a voltage waveform diagram in each of the embodiments. c,, C1, 7mm mmm: 7ndensa, Qal
@ Q'a21 Q bl * Qb2...
- Transistors, R,1 to Ra4. R,□~Rb4・
...Resistance, vCC...Power supply voltage, S...
Sb...Reset signal. Figure 2. Figure 5

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 直流電源ラインに直列抵抗を介して接続されたコンデン
サと、直流電源電圧と前記コンデンサの端子電圧とを比
較し、両型圧の差が所定値以上であるときにリセット信
号を出力する電圧比較回路とを有してるリセット回路。A voltage comparison circuit that compares a capacitor connected to a DC power supply line through a series resistor, and the DC power supply voltage and the terminal voltage of the capacitor, and outputs a reset signal when the difference between the two types of pressure is greater than a predetermined value. A reset circuit that has
JP11908781U 1981-08-11 1981-08-11 reset circuit Pending JPS5824838U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11908781U JPS5824838U (en) 1981-08-11 1981-08-11 reset circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11908781U JPS5824838U (en) 1981-08-11 1981-08-11 reset circuit

Publications (1)

Publication Number Publication Date
JPS5824838U true JPS5824838U (en) 1983-02-17

Family

ID=29913169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11908781U Pending JPS5824838U (en) 1981-08-11 1981-08-11 reset circuit

Country Status (1)

Country Link
JP (1) JPS5824838U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5085251A (en) * 1973-11-28 1975-07-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5085251A (en) * 1973-11-28 1975-07-09

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