JPS5822751U - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPS5822751U
JPS5822751U JP1981116939U JP11693981U JPS5822751U JP S5822751 U JPS5822751 U JP S5822751U JP 1981116939 U JP1981116939 U JP 1981116939U JP 11693981 U JP11693981 U JP 11693981U JP S5822751 U JPS5822751 U JP S5822751U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
semiconductor integrated
semiconductor wafer
sides
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981116939U
Other languages
English (en)
Inventor
正明 向井
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1981116939U priority Critical patent/JPS5822751U/ja
Publication of JPS5822751U publication Critical patent/JPS5822751U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来の回路素子を形成した半導体ウェーハの断
面図、第２図は本考案の一実施例の一部をなす半導体ウ
ェーハの断面図、第３図は本考案の一実施例の組立方法
を説明するための斜視図、第４図は本考案の一実施例の
要部平面図、第５図＼ ａ、　　ｂはそれぞれ第４図のＡ−Ａ’断面図およびＢ
−Ｂ’断面図である。 １・・・・・・Ｎ型シリコン・ウェーハ、２・・曲Ｐ型
ベース領域、３，４・・・・・・Ｎ型エミッタ領域、５
，６・・・・・・Ｐ型頭域、７・・・・・・共通端子、
１１・・・・・・Ｎ型シリコン・ウェーハ、１２．１２
’・・・・・・Ｐ型ベース領域、１３．１３’、１４．
１４’・・・・・・Ｎ型エミッタ領域、１５．１５’、
１６．１６’・・・・・・Ｐ型頭域、１７・・・・・・
共通端子、１８．１８’・・・・・・パッド、２０・・
・・・・リードフレーム、２１．２２・・・・・・内部
リード、２３・・・・・・半田、２４・・・・・・金属
線。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体ウェーハの両面にそれぞれ回路素子を形成し、配
    線し、該半導体ウェーハの両面の周縁部に接続用パッド
    を設け、該パッドに外部リードを接続した構造を有する
    ことを特徴とする半導体集積回路装置。
JP1981116939U 1981-08-05 1981-08-05 半導体集積回路装置 Pending JPS5822751U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981116939U JPS5822751U (ja) 1981-08-05 1981-08-05 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981116939U JPS5822751U (ja) 1981-08-05 1981-08-05 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPS5822751U true JPS5822751U (ja) 1983-02-12

Family

ID=29911147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981116939U Pending JPS5822751U (ja) 1981-08-05 1981-08-05 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS5822751U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013243328A (ja) * 2012-05-21 2013-12-05 Yoji Inada アーケード型半導体素子

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013243328A (ja) * 2012-05-21 2013-12-05 Yoji Inada アーケード型半導体素子

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