JPS58221521A - Reference potential generating circuit and input circuit using said generating circuit - Google Patents

Reference potential generating circuit and input circuit using said generating circuit

Info

Publication number
JPS58221521A
JPS58221521A JP57105120A JP10512082A JPS58221521A JP S58221521 A JPS58221521 A JP S58221521A JP 57105120 A JP57105120 A JP 57105120A JP 10512082 A JP10512082 A JP 10512082A JP S58221521 A JPS58221521 A JP S58221521A
Authority
JP
Japan
Prior art keywords
transistor
circuit
controlled
capacitor
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57105120A
Other languages
Japanese (ja)
Inventor
Yoshihisa Shioashi
塩足　慶久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57105120A priority Critical patent/JPS58221521A/en
Publication of JPS58221521A publication Critical patent/JPS58221521A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To realize small power consumption of titled circuits, by charging the 1st and 2nd capacitors with the power supply voltage and dividing the power supply voltage by the capacity ratio between those two capacitors to obtain the reference voltage. CONSTITUTION:A transistor TRQ3 and the 1st capacitor C1 are connected in series between a power supply VDD and an earth, and the TRQ3 is controlled by the 1st clock signal phi1. The 2nd capacitor C2 is connected between a joint between the TRQ3 and the capacitor C1 and the earth via MOSTRs Q4 and Q5 of transfer gate constitution which is controlled with the 2nd clock signal phi2 and its signal -phi2. The 2nd TRQ6 is connected in parallel across the capacitor C2 and controlled by the 1st control signal -phi1. Then the potential at the joint among the TRs Q4, Q5 and Q6 is supplied to the input terminal of one side of a comparator 12 as a reference potential Vref.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、例えば０ＭＯ８構成のマイクロコンピュー
タ等に最適な基準電位発生回路およびこの基準電位発生
回路を用いた入力回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a reference potential generation circuit suitable for, for example, a microcomputer with an 0MO8 configuration, and an input circuit using this reference potential generation circuit.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

一般に、基準電位発生回路は、′第１図に示すように構
成されている。すなわち、電源ｖＤＤと接地点間に抵抗
Ｒ１＋Ｒ１が直列接続され、この抵抗Ｒ１とＲ８・−と
の抵抗分割によって電源ｖＤＤ電圧を分圧し、抵抗Ｒ１
＊Ｒ１の接続点から所定の電圧ｖｒｅｆ　を得る。Generally, a reference potential generation circuit is constructed as shown in FIG. That is, a resistor R1+R1 is connected in series between the power supply vDD and the ground point, and the power supply vDD voltage is divided by resistance division between the resistors R1 and R8.
*Obtain a predetermined voltage vref from the connection point of R1.

しかし、上記のような構成の基準電位発生回路は、電源
ｖＤＤから接地点に貫通電流が流れるため、低消費電力
なＣＭ０８回路に適用すると消費電力が増加し、問題と
なる。However, in the reference potential generation circuit configured as described above, a through current flows from the power supply vDD to the ground point, so when applied to the low power consumption CM08 circuit, the power consumption increases, which poses a problem.

また、０Ｍ０８回路における入力回路として、第２図に
示すようなＣＭＯＳインバータ回路が用いられている。Further, as an input circuit in the 0M08 circuit, a CMOS inverter circuit as shown in FIG. 2 is used.

図において、ＱｌはＰチャネル型のＭＯＳ　）ランジス
タ、ＱｓはＮチャネル型のＭＯＳ　）ランジスタで、そ
れぞれのトランジスタＱ１−Ｑｍのダートに供給される
入力信号ＩＮの反転信号をトランジスタＱｔ　　、Ｑｓ
の接続点から出力信号ＯＵＴとして得る。In the figure, Ql is a P-channel type MOS () transistor, Qs is an N-channel type MOS () transistor, and the inverted signal of the input signal IN supplied to each of the transistors Q1-Qm is transferred to the transistors Qt, Qs.
It is obtained as an output signal OUT from the connection point.

しかし、上記のような構成の入力回路におい、ては、回
路しきい値Ｖｔｈ　ｔｉｐミルチャネルＭＯ８トランジ
スタのしきい値電圧Ｖよ、とＮチャネル型のＭＯ１ｉ＋
　）ランジスタのしきい値電圧ｖｔｈＮＫ依しまい、こ
の値を変えることが困難である。However, in the input circuit configured as above, the circuit threshold voltage Vth tip is the threshold voltage V of the mill-channel MO8 transistor, and the threshold voltage V of the N-channel type MO1i+
) It depends on the threshold voltage vthNK of the transistor, and it is difficult to change this value.

〔発明の目的〕[Purpose of the invention]

従って、この発明の第１の目的は、消費電力が少な（Ｃ
ＭＯ８回路に最適な基準電位発生回路を提供することで
ある。Therefore, the first object of the present invention is to reduce power consumption (C
An object of the present invention is to provide a reference potential generation circuit optimal for the MO8 circuit.

さらに、この発明の第２の目的は、上記基準電位発生回
路を用いて回路しきい値を自由に設定できる入力回路を
提供することである。Furthermore, a second object of the present invention is to provide an input circuit that can freely set a circuit threshold using the reference potential generation circuit described above.

〔発明の概要〕[Summary of the invention]

すなわち、この発明においては、電源電圧で第１．第２
のコンデンサを充電し、このコンデンサの容量比によっ
て電源電圧を分圧して基準電位を得る基準電位発生回路
を構成する。さらに、この基準電位発生回路の出力を比
較回路の一方の入力端に供給するとともに、この比較回
路の他方の入力端に入力信号を供給し、上記比を構成し
たものである。That is, in the present invention, the first. Second
A reference potential generation circuit is constructed which charges a capacitor and divides the power supply voltage according to the capacitance ratio of the capacitor to obtain a reference potential. Furthermore, the output of this reference potential generation circuit is supplied to one input terminal of a comparator circuit, and an input signal is supplied to the other input terminal of this comparator circuit to form the above ratio.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例について図面を参照して説明
する。第３図はその構成を示すもので、図において、１
１は基準電位発生回路、１２は比較回路である。すなわ
ち、電源ｖＤＤと接地点間に第１のトランジスタＱｓお
よび第１のコンデンサＣＩが直列接続され、上記トラン
ジスタＱｓは第１のクロック信号φ１で導通制御される
。上記トランジスタＱｓ　とコンデンサＣ１との接続点
と接地点間には、スイッチング手段として働き、第２の
クロツタ信号φ１およびその反転信号ｉ３で導通制御さ
れるトランスファダート構成のＭＯＳ　）ランジスタＱ
４＃ＱＩ　を介して第２のコンデンサＣ１が接続される
。上記コンデンサＣ，の両端には、第２のトランジスタ
Ｑ！が並列接続され、第１のクロック信号の反転信号１
１で導通制御される。そして、上記トランジスタＱｎｙ
Ｑｓ　とＱ−との接続点の電位が基準電位Ｖｒｅｆとし
て、比較回路１２の一方の入力端に供給される。上記比
較回路１２は、信号入力端子１３と上記基準電位発生回
路１１の出力端との間に、第３のクロック信号φ３およ
びその反転信号１ｍで導通制御される第３゜第４のトラ
ンジスタＱ７−Ｑ−が直列接続される。そして、上記ト
ランジスタＱｙｓＱｓの接続点の電位は、第３のコンデ
ンサＣｓを介して第１のインバータ回路１４とクロック
信号″ｉｒ３で導通制御される第５のトランジスタＱ＠
から成る増幅器に供給される。この増幅器の出力が、り
四ツク信号φ３で同期される第２のインバータ回路１５
によって保持される。An embodiment of the present invention will be described below with reference to the drawings. Figure 3 shows its configuration, and in the figure, 1
1 is a reference potential generation circuit, and 12 is a comparison circuit. That is, a first transistor Qs and a first capacitor CI are connected in series between a power supply vDD and a ground point, and the conduction of the transistor Qs is controlled by a first clock signal φ1. Between the connection point between the transistor Qs and the capacitor C1 and the ground point, there is a MOS transistor Q which functions as a switching means and has a transfer dart configuration and whose conduction is controlled by the second clock signal φ1 and its inverted signal i3.
A second capacitor C1 is connected via 4#QI. A second transistor Q! is connected across the capacitor C! are connected in parallel, and the inverted signal 1 of the first clock signal
1, conduction is controlled. And the above transistor Qny
The potential at the connection point between Qs and Q- is supplied to one input end of the comparison circuit 12 as the reference potential Vref. The comparator circuit 12 has a third and fourth transistor Q7- connected between the signal input terminal 13 and the output terminal of the reference potential generation circuit 11, whose conduction is controlled by the third clock signal φ3 and its inverted signal 1m. Q- are connected in series. The potential at the connection point of the transistor QysQs is connected to the first inverter circuit 14 via the third capacitor Cs and the fifth transistor Q@ whose conduction is controlled by the clock signal "ir3"
is supplied to an amplifier consisting of: The output of this amplifier is connected to a second inverter circuit 15 which is synchronized with a four-way signal φ3.
held by.

上記のような構成において、第４図のタイミングチャー
トを参照して動作を説明する。クロック信号φ１のロー
レベル時に、トランジスタＱｓがオン状態となシ、コン
デンサＣ１はハイレベルにグリチャージされる。この時
、クロック信号１１　のハイレベルによって、トランジ
スタＱ・がオン状態となシ、コンデンサＣ鵞の電レベル
、’ｆｉ囁”ｌ）”ローレベルになるト、トランジスタ
Ｑ４　ｙＱｓがオン状態となシ、コンデンサＣＩに充電
された電荷はコンデンサＣ，に分割される。そして、ク
ロック信号？ｓがノ・イレベルになると、コンデンサａ
ｔに充電された電荷が比較回路１２に供給される。従っ
て、上記コンデンサ０皿とＣ３との容量比の設定を変え
ることによシ、出力電圧ｖｒ＠ｆのレベルを自由に設定
できる。出力電圧ｖｒ＠ｆは下式（１）で示される。In the above configuration, the operation will be explained with reference to the timing chart of FIG. When the clock signal φ1 is at a low level, the transistor Qs is turned on and the capacitor C1 is charged to a high level. At this time, due to the high level of the clock signal 11, the transistor Q is turned on, the voltage level of the capacitor C becomes low level, and the transistor Q4 and Qs are turned on. , the charge charged in capacitor CI is divided into capacitor C,. And the clock signal? When s reaches the no level, capacitor a
The charges charged at time t are supplied to the comparator circuit 12. Therefore, by changing the setting of the capacitance ratio between the capacitor 0 and C3, the level of the output voltage vr@f can be freely set. The output voltage vr@f is expressed by the following formula (1).

次に、比較回路１２の動作について説明する。Next, the operation of the comparison circuit 12 will be explained.

まず、クロック信号″′ｉ；３のハイレベルによりて第
５のトランジスタＱ―をオン状態とし、第１のインバー
タ回路１４０入出力端の電位を同じレベルとし、このイ
ンバータ回路１４のしきい値電圧ｖｔｈをハイレベルと
ローレベルとの間の所定のレベルとする。この時、第３
のコンデンサＣ３には基準電位ｖｒｄに対応した電荷が
充電される。次に、クロック信号７３がローレベル、φ
３がハイレベルとなると、入力端子１３から入力信号Ｉ
ＮがトランジスタＱ７を介してコンデンサＣＩに供給さ
れる。入力信号ＩＮが基準電圧Ｖｒｅｆよル大きいとイ
ンバータ回路１４の出力はローレベルとなり、第２のイ
ンバータ回路１５を介してハイレベルの出力信号ＯＵＴ
を得る。また、入力信号ＩＮが基準電圧ｖｒｅｆより小
さい場合は、インバータ回路１４の出力はハイレベルと
なシ、インバータ回路１５を介してローレベルの出力信
号ＯＵＴを得る。従って、基準電圧Ｖｒｅｆの値を変え
ることによ勺、入力回路の回路しきい値を自由に設定で
きる。First, the fifth transistor Q- is turned on by the high level of the clock signal ``'i; Let vth be a predetermined level between high level and low level.At this time, the third
The capacitor C3 is charged with an electric charge corresponding to the reference potential vrd. Next, the clock signal 73 is at a low level, φ
3 becomes high level, the input signal I is output from the input terminal 13.
N is supplied to capacitor CI via transistor Q7. When the input signal IN is greater than the reference voltage Vref, the output of the inverter circuit 14 becomes low level, and the output signal OUT of high level is output via the second inverter circuit 15.
get. Further, when the input signal IN is smaller than the reference voltage vref, the output of the inverter circuit 14 is not at a high level, and an output signal OUT at a low level is obtained via the inverter circuit 15. Therefore, by changing the value of the reference voltage Vref, the circuit threshold of the input circuit can be freely set.

今、上記第３図の入力回路の回路しきい値を０、　Ｉ　
Ｖ、Ｄに設定しようとすれば、下式（２）に示すように
コンデンサＣｉ、Ｃ，の容量比を設定すれば良い。Now, set the circuit threshold value of the input circuit in Figure 3 above to 0, I
If it is desired to set the capacitors to V and D, the capacitance ratio of the capacitors Ci and C can be set as shown in equation (2) below.

ＣＩ ０、１　ＶＤ、　ｗ　；　ｖＤ、　　　　　　・・・（
２）露□Ｖ　　　　　　・・・（２′） α＋１１）Ｄ ｌ ここで「αツー」である。CI 0, 1 VD, w; vD, ...(
2) Dew □V...(2') α+11)D l Here, it is "α2".

３ 上式（２′）よシα＝−となる。すなわち、「Ｃ１：Ｃ
１＝１：９Ｊに設定すれば良い。3 According to the above equation (2'), α=-. In other words, “C1:C
It is sufficient to set it to 1=1:9J.

上述したように、回路しきい値はコンデンサＣ１とＣＩ
との比と、電源Ｖ□電圧だけで決定されるので、コンデ
ンサＣＩとＣＩ　とを同一工程で形成すれば、Ｐチャネ
ル型のトランジスタのしきい値電圧ｖｔｈＰおよびＮチ
ャネル型のトランジスタのしきい値電圧ｖｔｈＨには無
関係である。As mentioned above, the circuit threshold is determined by capacitors C1 and CI
Since it is determined only by the ratio of It is unrelated to voltage vthH.

また、比較回路１２も原理的にｖ　　ｖ　にはｔｈＰ　
　’　　　ｔｈＮ 左右されない。Also, in principle, the comparator circuit 12 also has thP for v v
' thN Not affected.

なお、スイッチング手段として働くトランジスタＱａ−
Ｑｓ’にトランス電ツシ璽ングート構成としたが、いず
れか一方のトランジスタのみでも良いのはもちろんであ
る。Note that the transistor Qa- serving as a switching means
Although Qs' has a transformer transistor configuration, it is of course possible to use only one of the transistors.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明によれば、消費電力が少な
（ＣＭＯ８回路に最適な基準電位発生回路が得られる。As described above, according to the present invention, a reference potential generation circuit with low power consumption (optimal for the CMO8 circuit) can be obtained.

さらに、この発明によれば、上記基準電位発生回路を用
いて回路しきい値を自由に設定できる入力回路が得られ
る・Furthermore, according to the present invention, an input circuit can be obtained in which the circuit threshold value can be freely set using the reference potential generation circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の基準電位発生回路を示す図、第２図は０
Ｍ０８回路における従来の入力回路を示す図、第３図は
この発明の一実施例に係る基準電位発生回路およびこれ
を用いた入力回路を示す図、第４図は上記第３図の回路
の動作を説明するためのタイミングチャートである。 １ノ・・・基準電位発生回路、１２・・・比較回路、１
３・・・入力端子、１４．１５・・・インバータ回路、
φｌｅ９’ｌ＋φ雪　、ｉ鵞　、φ３　、￥３・・・ク
ロック信号、Ｑｓ〜Ｑｓ　・・・トランジスタ％Ｃ１〜
ＣＩ・・・コンデンサ。 出願人代理人　　弁理士　鈴　江　武　彦第１図　　　
第２図 第３図 ２ 」 １０８− 第４図 ＵＴFigure 1 is a diagram showing a conventional reference potential generation circuit, and Figure 2 is a diagram showing a conventional reference potential generation circuit.
FIG. 3 is a diagram showing a conventional input circuit in the M08 circuit, FIG. 3 is a diagram showing a reference potential generation circuit according to an embodiment of the present invention and an input circuit using the same, and FIG. 4 is an operation of the circuit shown in FIG. 3 above. 2 is a timing chart for explaining. 1 No...Reference potential generation circuit, 12... Comparison circuit, 1
3...Input terminal, 14.15...Inverter circuit,
φle9'l+φyuki, i鵞, φ3, ¥3...clock signal, Qs~Qs...transistor%C1~
CI... Capacitor. Applicant's agent Patent attorney Takehiko Suzue Figure 1
Figure 2 Figure 3 Figure 2 108- Figure 4 UT

Claims (1)

【特許請求の範囲】 （リ　電源と接地点間に接続され第１のクロック信号で
導通制御される第１のトランジスタおよび第１のコンデ
ンサから成る直列回路と、上記トランジスタとコンデン
サとの接続点と接地点間に第２のクロック信号で開閉制
御されるスイッチング手段を介して並列接続される第２
のコンデンサおよび上記第１のクロック信号の反転信号
で導通制御される第２のトランジスタとを具備し、上記
第１．第２のトランジスタはそれぞれ逆極性のトランジ
スタから成シ、上記スイッチング手段と第２のトランジ
スタとの接続点から出力を得るように構成したことを特
徴とする基準電位発生回路。 （２）上記スイッチング手段は、ｔ！ｇ２のクロック信
号およびその反転信号で導通制御されるトランスファ、
ｅ−）構成のＭＯＳ　）ランジスタから成ることを特徴
とする特許請求の範囲第１項記載の基準電位発生回路。 （３）電源と接地点間に接続され第１のり四ツク信号で
導通制御される第１のトランジスタおよび第１のコンデ
ンサから成る直列回路と、上記トランジスタとコンデン
サとの接続点と接地点間に第２のり四ツク信号で開閉制
御されるスイッチング手段を介して並列接続される第２
のコンデンサおよび上記第１のクロック信号の反転信号
で導通制御される第２のトランジスタとから成る基準電
位発生回路と、この基準電位発生回路の出力と入力信号
とを比較する比較回路とを具備することを特徴とする入
力回路。 （４）上記スイッチング手段は１、第２のクロック信号
およびその反転信号で導通制御されるトランス７アグー
ト構成のＭｏｓ　）ランジスタから成ることを特徴とす
る特許請求の範囲第３項記載の入力回路。 （５）上記比較回路は、スイッチング手段と第２のトラ
ンジスタとの接続点と信号入力端子間に直列接続され第
３のクロック信号およびその反転信号で導通制御される
第３．第４のトランジスタと、上記第３．第４のトラン
ジスタの接続点と出力端子との間に直列接続される第３
のコンデンサおよび第１．第２のインバータ回路と、上
記第１のインバータ回路の入出力端間に接続され第３の
クロック信号の反転信号で導通制御される第５のトラン
ジスタとを具備し、上記第２のインバータ回路紘第３の
クロック信号で同期されたクロックドインバータ回路か
ら成ることを特徴とする特許請求の範囲第３項記載の入
力回路。[Scope of claims] A second circuit connected in parallel between the grounding points via a switching means that is controlled to open and close by a second clock signal.
and a second transistor whose conduction is controlled by an inverted signal of the first clock signal. 2. A reference potential generation circuit characterized in that each of the second transistors is composed of transistors having opposite polarities, and the output is obtained from a connection point between the switching means and the second transistor. (2) The switching means has t! a transfer whose conduction is controlled by the clock signal of g2 and its inverted signal;
2. The reference potential generation circuit according to claim 1, wherein the reference potential generation circuit comprises a MOS transistor having an e-) configuration. (3) A series circuit consisting of a first transistor and a first capacitor connected between a power supply and a ground point and whose conduction is controlled by a first cross signal, and a connection point between the transistor and the capacitor and the ground point. The second
a reference potential generation circuit comprising a capacitor and a second transistor whose conduction is controlled by an inverted signal of the first clock signal; and a comparison circuit that compares the output of the reference potential generation circuit with an input signal. An input circuit characterized by: (4) The input circuit according to claim 3, wherein said switching means comprises a Mos transistor having a transformer (7) active configuration whose conduction is controlled by a second clock signal and its inverted signal. (5) The comparison circuit includes a third transistor connected in series between a connection point between the switching means and the second transistor and a signal input terminal, and whose conduction is controlled by a third clock signal and its inverted signal. a fourth transistor; and the third transistor. A third transistor connected in series between the connection point of the fourth transistor and the output terminal
capacitor and the first capacitor. The second inverter circuit includes a second inverter circuit, and a fifth transistor connected between the input and output terminals of the first inverter circuit and whose conduction is controlled by an inverted signal of the third clock signal. 4. The input circuit according to claim 3, comprising a clocked inverter circuit synchronized with a third clock signal.
JP57105120A 1982-06-18 1982-06-18 Reference potential generating circuit and input circuit using said generating circuit Pending JPS58221521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57105120A JPS58221521A (en) 1982-06-18 1982-06-18 Reference potential generating circuit and input circuit using said generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57105120A JPS58221521A (en) 1982-06-18 1982-06-18 Reference potential generating circuit and input circuit using said generating circuit

Publications (1)

Publication Number Publication Date
JPS58221521A true JPS58221521A (en) 1983-12-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP57105120A Pending JPS58221521A (en) 1982-06-18 1982-06-18 Reference potential generating circuit and input circuit using said generating circuit

Country Status (1)

Country Link
JP (1) JPS58221521A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2628547A1 (en) * 1988-03-09 1989-09-15 Sgs Thomson Microelectronics STABILIZED GENERATOR FOR PROVIDING MOS TRANSISTOR THRESHOLD

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5784614A (en) * 1980-09-22 1982-05-27 American Micro Syst Double channel filter with condenser switched digitally
JPS5871731A (en) * 1981-10-02 1983-04-28 フエアチアイルド・カメラ・アンド・インスルメント・コ−ポレ−シヨン Dynamic ttl input comparator for c-mos device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5784614A (en) * 1980-09-22 1982-05-27 American Micro Syst Double channel filter with condenser switched digitally
JPS5871731A (en) * 1981-10-02 1983-04-28 フエアチアイルド・カメラ・アンド・インスルメント・コ−ポレ−シヨン Dynamic ttl input comparator for c-mos device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2628547A1 (en) * 1988-03-09 1989-09-15 Sgs Thomson Microelectronics STABILIZED GENERATOR FOR PROVIDING MOS TRANSISTOR THRESHOLD
US4954728A (en) * 1988-03-09 1990-09-04 Sgs-Thomson Microelectronics S.A. Stabilized generator for supplying a threshold voltage to a MOS transistor

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