JPS58207655A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58207655A
JPS58207655A JP57089657A JP8965782A JPS58207655A JP S58207655 A JPS58207655 A JP S58207655A JP 57089657 A JP57089657 A JP 57089657A JP 8965782 A JP8965782 A JP 8965782A JP S58207655 A JPS58207655 A JP S58207655A
Authority
JP
Japan
Prior art keywords
pellet
base
inner lead
lead parts
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57089657A
Other languages
Japanese (ja)
Other versions
JPH0473299B2 (en
Inventor
Takeshi Komaru
小丸　健
Tetsuo Matsumoto
哲郎 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57089657A priority Critical patent/JPS58207655A/en
Publication of JPS58207655A publication Critical patent/JPS58207655A/en
Publication of JPH0473299B2 publication Critical patent/JPH0473299B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive the improvement of mounting density and the thin film formation of a device by a method wherein the wirings to connect inner lead parts and outer lead parts are formed at the position of pellet fixing of a base, and the pellet is fixed on these wirings with insulation adhesive. CONSTITUTION:Since the inner lead parts 12 formed in two arrays on the upper surface of the base 10 are conducted to the outer lead parts 13 arranged in four peripheries on the lower surface of the base respectively via the wirings 14a, 14b, and 14c, the mounting of a chip carrier can be performed entirely in the same manner as a conventional one, if the pellet 11 is connected to these inner lead parts 12 by wires 16. In this case, the wirings 14b for connecting the inner lead parts 12 and the outer lead parts 13 can be freely arranged on the base upper surface, therefore the design even of a single layer type can be performed in the same manner as of a multi-layer type. Since the pellet 11 is fixed on the base 10 with the insulation adhesive 15, the pellet 11 and the wiring 14b do not short-circuit. Accordingly, the mounting density of chip carrier can be enhanced in spite of being a single layer type, and the device can be formed into a thin type.

Description

【発明の詳細な説明】 本発明は実装密夏の改善を図ったチップキャリア型の半
導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a chip carrier type semiconductor device which is intended to improve packaging density.

半導体装置のバックージめ一つにテップキャリアがあり
、特に実装密度の改善、特性向上の点からセラミックを
使用した積層型、牟層型のものが使用されている。これ
らのチップキャリアは、半導体素子ペレットのｔ極バッ
ドにワイヤ接続を行なうインナリード部と外部導出用の
アクタリード部との間の接続を行なうメタライズ配線に
構造上の相違は存在するものの、いずれもセラミックベ
ースの上面中央にＡｕメタライズを形成し、このＡｕメ
タライズ上にペレットを例えばＡｕＳｉ共晶を利用して
ベレット付するようにしている点では同じである。した
がって、インナリード部とアウタリード部とを接続する
メタライズ配線は、前記Ａｌｌメタライズを避すて配設
しなければならず、チップキャリアの設計、製造を困離
なものにする原因の一つとなっている。One of the backbones of semiconductor devices is a tip carrier, and in particular, ceramic-based multilayer and multilayer types are used from the viewpoint of improving packaging density and improving characteristics. These chip carriers are all made of ceramic, although there are structural differences in the metallized wiring that connects the inner lead part that connects the wire to the T-pole pad of the semiconductor element pellet and the external lead part. They are the same in that an Au metallization is formed at the center of the upper surface of the base, and pellets are attached to the Au metallization using, for example, AuSi eutectic. Therefore, the metallized wiring connecting the inner lead part and the outer lead part must be arranged avoiding the above-mentioned All metallization, which is one of the reasons for making the design and manufacturing of the chip carrier difficult. There is.

例えば、第１図は単層型チップキャリアｌであり、略正
方形に形成したセラミックベース２の上面中央にＡｕメ
タライズ３を形成しここにペレット４を固着する。また
、Ａｕメタライズ３の周囲には複数個のインナーリード
部５を配設し、前記ベレット４との間にワイヤ６を接続
してｔ気的な導通を図っている、そして、このインナリ
ード部５はセラミックベース２の下ｍ１四周辺に配設し
たアウタリード部７に配線接続し、このアウタリード部
７を介して図外の回路に実装接続するようにしている。For example, FIG. 1 shows a single-layer chip carrier 1, in which an Au metallization 3 is formed at the center of the upper surface of a ceramic base 2 formed into a substantially square shape, and a pellet 4 is fixed thereto. Further, a plurality of inner lead parts 5 are disposed around the Au metallization 3, and a wire 6 is connected between them and the pellet 4 to achieve electrical conduction. 5 is wire-connected to an outer lead portion 7 disposed around the bottom m1 of the ceramic base 2, and is mounted and connected to a circuit (not shown) via the outer lead portion 7.

セラミックベース上にはレジン等の封止材を設けること
は言うまでもない。Needless to say, a sealing material such as resin is provided on the ceramic base.

したがってこのようなチップキャリアにおいて、Ａｉｌ
述のインナリード部５とアウタリード部７の上下面位置
にずれが生じている場合には、両者を接続する配線はＡ
ｕメタライズ３の周囲のセラミックベース２上に平面方
向に延設した状態で行なわなければならない。このため
、第２図に示す最近のメモリ用ベレット４Ａのように電
極バッド８を長方形ベレットの短辺に沿って配置するも
のにおいては、インナリード部５をも同図のようにセラ
ミックベース２の２辺に沿って配設しなければならず、
これらインナリード□部５とセラミンクベース２の下面
四辺に配設したアクタリード部７との配線９の数が多く
なってその配設が困難になる。Therefore, in such a chip carrier, Ail
If there is a misalignment in the upper and lower surface positions of the inner lead part 5 and outer lead part 7, the wiring connecting them is A.
This must be done while extending in the plane direction on the ceramic base 2 around the u metallization 3. For this reason, in a recent memory pellet 4A shown in FIG. 2 in which the electrode pads 8 are arranged along the short sides of the rectangular pellet, the inner lead portion 5 is also attached to the ceramic base 2 as shown in the same figure. Must be placed along two sides,
The number of wiring lines 9 between these inner lead square parts 5 and the actor lead parts 7 arranged on the four sides of the lower surface of the ceramic base 2 increases, making it difficult to arrange them.

場合によっては、ＡＬ＋メタライズ３周囲のスペースが
小さすぎ、配線が不可能な場合もある。In some cases, the space around the AL+metalization 3 is so small that wiring is impossible.

これに対し、多層型のチップキャリアではこのような場
合でも配線を多層に形成して各配線を厚さ方向に絶縁す
ることで可能にしているが、構造が極めて複雑になる上
に製造が困難になってコスト高になり、かつ一方ではチ
ップキャリア厚が太き（なって薄型実装には向かないと
いう不具合が生じ℃いる。Multilayer chip carriers, on the other hand, make this possible by forming wiring in multiple layers and insulating each wiring in the thickness direction, but this makes the structure extremely complex and difficult to manufacture. This results in higher costs, and on the other hand, there is the problem that the chip carrier is thick (which makes it unsuitable for thin packaging).

したがって本発明の目的はインナリード部とアウタリー
ド部との間の配線の自由度を高めて単層型チップキャリ
アにおける種々のベレットのパッケージを可能にし、こ
れにより実装密度の向上を図９か、つ装置の薄型化、低
コスト化を達成することができる半導体装置を提供する
ことにある。Therefore, an object of the present invention is to increase the degree of freedom in wiring between the inner lead part and the outer lead part, and to enable packaging of various pellets in a single-layer chip carrier, thereby improving the packaging density as shown in FIG. An object of the present invention is to provide a semiconductor device that can achieve a reduction in device thickness and cost.

この目的を達成するために本発明は、ベースの上面中央
部はＡＬ＋メタライズを形成せずその代りに核部に配線
を施し、かつベレットはこの配線上に絶縁性接着剤を用
いて固着する構成とするものである。In order to achieve this object, the present invention has a structure in which no AL+ metallization is formed on the center part of the upper surface of the base, but instead wiring is applied to the core part, and the pellet is fixed onto this wiring using an insulating adhesive. That is.

以丁、本発明を図示の実施例により説明１−る。The present invention will now be explained with reference to the illustrated embodiments.

第３図は本発明の半導体装質の一部破断乎面図、第４図
はその破断側面図である。図において、１０は例えばセ
ラミンクからなる略正方形のベースで、その上面には半
導体素子ベレッ）１１を中央に固着しく４る平面的な余
裕を取った上で対向する２辺１ｉ置には夫々複数個のイ
ンナリード部１２をＡｕメタライズにて形成している。FIG. 3 is a partially cutaway plan view of the semiconductor device of the present invention, and FIG. 4 is a cutaway side view thereof. In the figure, reference numeral 10 denotes a substantially square base made of ceramic, for example, and on its upper surface, a semiconductor element bezel (11) is firmly fixed in the center. The inner lead portions 12 are made of Au metallization.

また、ベース１０の下面の４′辺位置には少なくとも前
記インナリード部１２に対応する数のアウタリード部１
３を設けている。そして、前記インナリード部１２とア
ウタリード部１３とは夫々対応するものを配線１４によ
って導通接続しているが、この場合上下に対応位置する
両リード部、例えばリード部１２ａと１３ａではベース
１００周縁に上下方向に形成した配線１４ａにて直接的
に接続している。一方、中 上下に対応位置しないリード部１２ｂと１３ｂでは、ベ
ースｌＯの上面中央部にＡｕメタライズによって延設形
成した配線１４ｂと、この配線１４ｂをベース周縁にお
いて上下方向に導通する配線１４Ｃとで両者を接続して
いる。そして、ベレノ）１１は絶Ｆ＋、Ｖｔの接着剤１
５、例えばポリイミド樹脂等の有機月利を使用してｒｉ
ｉｌ記配線１４ｂの上側にこれらとは絶縁状態を保って
固着し、かつその′成極バッドｌｌａと前記インナリー
ド部１２とをワイヤ１６にて接続している。勿論、この
ベレット１１はその短辺側にのみ設けたｉｉＬ＆バッド
１１ａを前記インナリード部１２に対向配置するもので
あることは言うまでもない。また、このように実装した
上でベースｌ　Ｏ上にはボッティング等によってレジン
を滴下し、ベレット１１１ワイヤ１６、インナリード部
１２等を封止することも言うまでもない。Further, at least a number of outer lead parts 1 corresponding to the inner lead parts 12 are provided at the 4' side position of the lower surface of the base 10.
There are 3. The corresponding inner lead portions 12 and outer lead portions 13 are electrically connected to each other by wiring 14, but in this case, both lead portions correspondingly located above and below, for example lead portions 12a and 13a, are connected to the periphery of the base 100. They are directly connected by wiring 14a formed in the vertical direction. On the other hand, in the lead portions 12b and 13b which are not located in the upper and lower middle positions, a wiring 14b extending from the center of the upper surface of the base 1O by Au metallization and a wiring 14C connecting this wiring 14b in the vertical direction at the periphery of the base are connected to each other. are connected. And Veleno) 11 is absolute F+, Vt adhesive 1
5. For example, using organic resin such as polyimide resin
It is fixed to the upper side of the wiring 14b while being insulated from these, and the polarization pad lla and the inner lead portion 12 are connected by a wire 16. Of course, it goes without saying that this bellet 11 has the iiL & pad 11a provided only on its short side facing the inner lead portion 12. It goes without saying that after mounting in this way, resin is dropped onto the base 10 by botting or the like to seal the bullet 111, the wire 16, the inner lead portion 12, etc.

以上の構成によれば、ベース１０の上面に２列に形成し
たインナリード部１２はベースの下面において四周囲に
配設したアウタリード部１３に夫々配線１４ａや１４ｂ
、１４Ｃを介して導通しているので、ベレット１１をこ
れらインナリード部１２にワイヤ１６接続すればチップ
キャリアの実装は従来のものと全く同様に行なうことが
できる。According to the above configuration, the inner lead portions 12 formed in two rows on the upper surface of the base 10 are connected to the outer lead portions 13 arranged around the four peripheries on the lower surface of the base, respectively.
, 14C, the chip carrier can be mounted in exactly the same manner as the conventional one by connecting the bullet 11 to these inner lead portions 12 with the wires 16.

そして、この場合インナリード部１２とアウタリード部
１３の接続用の配線１４ｂはペース上面に自由に自由に
配設できるので、単層型であっても多層型と同様に設計
できる。しかしながら、ベレット１１は絶縁性接着剤１
５にてペース１ｏ上に固着しているので、ベレット１１
と配線１４ｂとが短絡することはない。したかって、単
層型でありながらチップキャリアの実装密度を高めるこ
とができ、かつ装置全体の構造を開学がっ薄型に形成す
ることができる。In this case, the wiring 14b for connecting the inner lead part 12 and the outer lead part 13 can be freely arranged on the upper surface of the paste, so that even a single layer type can be designed in the same way as a multilayer type. However, the insulating adhesive 1
At 5, he was stuck on pace 1o, so Beret was 11.
There will be no short circuit between the wire 14b and the wire 14b. Therefore, although it is a single layer type, the packaging density of the chip carrier can be increased, and the overall structure of the device can be formed to be thin and simple.

ここで、前記接着剤１５中に若干の金属粉を混入してそ
の絶縁性を失なわない範囲で接着剤の熱伝導率を高め、
これによりベレットの放熱性を高めるようにしてもよい
。また、接着剤にはシート状のものを使用し、このシー
ト状接着剤（材）を介して配線１４ｂとベレット１１と
を絶縁しながラヘレットを固着するようにしてもよい。Here, some metal powder is mixed into the adhesive 15 to increase the thermal conductivity of the adhesive within a range without losing its insulating properties.
This may improve the heat dissipation of the pellet. Alternatively, a sheet-like adhesive may be used, and the lachelette may be fixed while insulating the wiring 14b and the bellet 11 via this sheet-like adhesive (material).

なお、゛前記配線１４ｂはインナリード部１２と一体的
にＡｕメタライズにて形成することが工程上有効である
が、別工程であるいは別材質にて形成してもよい。また
、配線１４ｂのパターンやインナリード部１２の配列は
図示の実施例に限られるものでなく、ベレット１１のｉ
ｌ＝　＆パッドの配列に対応して）・口々製形すること
ができる。Although it is effective in terms of process to form the wiring 14b integrally with the inner lead portion 12 using Au metallization, it may be formed in a separate process or from a different material. Furthermore, the pattern of the wiring 14b and the arrangement of the inner lead portions 12 are not limited to the illustrated embodiment;
l= & Corresponding to the pad arrangement)・Can be shaped from mouth to mouth.

以上のように本発明の半導体装置によれば、ペースの上
面にはベレット固層用のメタライズを設けずにインナリ
ード部とアウタリード部の接絞用配線を延設し、ベレッ
トは絶縁性接着剤にてペース上に固着しているので、配
線の自由度を高めて任意なインナリー　ド部の配列を可
能にし、これにより装置の実装密度の向上を図ると共に
チップキャリアの構造を１￥Ｉ］略化し、製造の容易化
および低コスト化を図りかつ一方では装置の薄型化を実
現−ｆることができるという効果を喫する。As described above, according to the semiconductor device of the present invention, the wiring for connecting the inner lead part and the outer lead part is extended without providing metallization for pellet solidification on the upper surface of the pad, and the pellet is made of an insulating adhesive. Since it is fixed on the chip surface, it increases the degree of freedom in wiring and makes it possible to arrange the inner leads as desired.This improves the packaging density of the device and also improves the structure of the chip carrier. This has the effect of making the device easier to manufacture and lower in cost, while at the same time making the device thinner.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は一般的なチップキャリアを用いた半導体装置の
平面図、第２図は従来のチップキャリアの平面図、第３
図は本発明装置の破断平面図、第４図はその破断側面図
である。 １（）・・・ペース、１１・・・ベレット、１２１１２
ａｌ］、　２　ｂ　＝・インナリード部、１３．１３ａ
、１３ｂ・・・アウタリード部、１４，１４ａ、１４ｂ
ｌ１４ｃ・・・配線、１５・・・接着剤、１６・・・ワ
イヤ、１７・・・レジン。 代理人　弁理士　　薄　１）利　幸 ＝２４ンFig. 1 is a plan view of a semiconductor device using a general chip carrier, Fig. 2 is a plan view of a conventional chip carrier, and Fig. 3 is a plan view of a semiconductor device using a general chip carrier.
The figure is a cutaway plan view of the device of the present invention, and FIG. 4 is a cutaway side view thereof. 1()...Pace, 11...Berrett, 12112
al], 2 b = Inner lead part, 13.13a
, 13b...outer lead part, 14, 14a, 14b
l14c...Wiring, 15...Adhesive, 16...Wire, 17...Resin. Agent Patent Attorney Susuki 1) Yuki Toshi = 24 N

Claims (1)

【特許請求の範囲】 １、方形のベースの上面にペレットを固着すると共にこ
のペレットと祇気的な接続を行なうインナリード部を形
成し、下面には四周辺にアウタリード部を配設してなる
チップキャリア型の半導体装置において、前記ベースの
ペレット固着位置にはペレット固着用のメタライズを設
ける代りに前記インナリード部とアウタリード部を接続
する配線を形成し、前記ペレットはこの配線上に絶縁性
接着剤′にて固着したことを特徴とする半導体装置。 ２、インナリード部はベースの対向する２辺に旧って配
列し、ペレットには対向する２辺に沿って′／Ｉ！極パ
電極を形成してなる特許請求の範囲第１項記載の半導体
装置。[Scope of Claims] 1. A pellet is fixed to the upper surface of a rectangular base, and an inner lead portion is formed to make a connection with the pellet, and outer lead portions are arranged around the four peripheries on the lower surface. In a chip carrier type semiconductor device, instead of providing metallization for pellet fixation at the pellet fixation position of the base, a wiring connecting the inner lead part and the outer lead part is formed, and the pellet is attached with insulating adhesive on this wiring. 1. A semiconductor device, characterized in that it is fixed with an agent. 2. The inner lead parts are arranged on the two opposite sides of the base, and the pellet has a '/I!' along the two opposite sides. A semiconductor device according to claim 1, which comprises a polar electrode.
JP57089657A 1982-05-28 1982-05-28 Semiconductor device Granted JPS58207655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57089657A JPS58207655A (en) 1982-05-28 1982-05-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57089657A JPS58207655A (en) 1982-05-28 1982-05-28 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS58207655A true JPS58207655A (en) 1983-12-03
JPH0473299B2 JPH0473299B2 (en) 1992-11-20

Family

ID=13976821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57089657A Granted JPS58207655A (en) 1982-05-28 1982-05-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58207655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03171759A (en) * 1989-11-30 1991-07-25 Toshiba Corp Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5190473A (en) * 1975-02-07 1976-08-07
JPS5645069A (en) * 1979-09-20 1981-04-24 Nec Corp Hybrid integrated circuit device
JPS5842940U (en) * 1981-09-16 1983-03-23 株式会社村田製作所 Hybrid integrated circuit device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842940B2 (en) * 1979-01-24 1983-09-22 株式会社日立メデイコ Ionization chamber type X-ray detector and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5190473A (en) * 1975-02-07 1976-08-07
JPS5645069A (en) * 1979-09-20 1981-04-24 Nec Corp Hybrid integrated circuit device
JPS5842940U (en) * 1981-09-16 1983-03-23 株式会社村田製作所 Hybrid integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03171759A (en) * 1989-11-30 1991-07-25 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0473299B2 (en) 1992-11-20

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