JPS58204311A - Detector for absolute position - Google Patents
Detector for absolute positionInfo
- Publication number
- JPS58204311A JPS58204311A JP8756082A JP8756082A JPS58204311A JP S58204311 A JPS58204311 A JP S58204311A JP 8756082 A JP8756082 A JP 8756082A JP 8756082 A JP8756082 A JP 8756082A JP S58204311 A JPS58204311 A JP S58204311A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- resolver
- signal
- phase
- absolute position
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
- G01D5/244—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains
- G01D5/247—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains using time shifts of pulses
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、例えば移動機械の基準点からの位置を検出
する絶対位置検出装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an absolute position detection device for detecting the position of a mobile machine from a reference point, for example.
従来の絶対位置検出装置には例えば第１図ないし第３図
に示すものがある。すなわち、第１図は側副装置のブロ
ック図で、図において、１ａ、１ｂは移動機械の車輪の
回転角度を検出する上位。2. Description of the Related Art Conventional absolute position detection devices include those shown in FIGS. 1 to 3, for example. That is, FIG. 1 is a block diagram of the collateral device, and in the figure, 1a and 1b are upper units that detect the rotation angle of the wheels of the mobile machine.
下位のレゾルバ移相機、２はこのレゾルバ移相機ｌａ、
ｌｂの入力軸を適当な伝達比で結合する回転伝達機構で
ある。３はレゾルバ移相機１ａ、１ｂに励振信号４を与
える励振回路を示し、この励振回路３は、パルス発振器
５、このパルス発振器５のパルス信号６を分周する分周
器７およびこの分周器７の励振パルス８を増幅してレゾ
ルバ移相機１ａ、ｌｂを励振する増幅器９によって構成
される。１０はレゾルバ移相機１ａ、ｌｂの励振信号４
とそれぞれの移相信号１１ａ、１１ｂとの位相差を検出
する位相差検出回路を示し、この位相差検出回路１０は
、レゾルバ移相機１ａｔｔｂのそれぞれの移相信号１１
ａ、Ｉｌｂを増幅する増幅器１２ａ、１２ｂ、コノ増幅
器１２ａ、１２ｂのそれぞれの増幅信号１３ａ、１３ｂ
を矩形波に整形するシュミット回路１４ａ、１４ｂ、こ
のシュミット回路１４ａ、１４ｂのそれぞれの矩形信号
１５ａ、１５ｂの立上がりを微分し、微分パルス１６ａ
、１５ｂとする微分回路１７ａ、１７ｂ、前記パルス発
振器５のパルス信号６によりカウントする２進カウンタ
１８および前記微分回路１７ａ、１７ｂのそれぞれの微
分パルス１６ａ、１６ｂにより、この２進カウンタ１８
の内容を記憶する記憶回路１９ａ、１９ｂによって構成
される。Lower resolver phase shifter, 2 is this resolver phase shifter la,
This is a rotation transmission mechanism that connects lb. input shafts at an appropriate transmission ratio. 3 indicates an excitation circuit that provides an excitation signal 4 to the resolver phase shifters 1a and 1b, and this excitation circuit 3 includes a pulse oscillator 5, a frequency divider 7 that divides the frequency of the pulse signal 6 of this pulse oscillator 5, and this frequency divider. It is constituted by an amplifier 9 that amplifies the excitation pulse 8 of 7 and excites the resolver phase shifters 1a and lb. 10 is an excitation signal 4 for the resolver phase shifters 1a and lb.
The phase difference detection circuit 10 detects the phase difference between the phase shift signals 11a and 11b of the resolver phase shifter 1attb.
a, Ilb, and amplified signals 13a and 13b of the amplifiers 12a and 12b, respectively, of the Kono amplifiers 12a and 12b.
Schmitt circuits 14a and 14b that shape the signal into a rectangular wave, differentiate the rising edges of the respective rectangular signals 15a and 15b of these Schmitt circuits 14a and 14b, and generate a differentiated pulse 16a.
, 15b, a binary counter 18 that counts based on the pulse signal 6 of the pulse oscillator 5, and the differential pulses 16a, 16b of the differentiating circuits 17a, 17b.
It is constituted by memory circuits 19a and 19b that store the contents of.
２０はレゾルバ移相機１ ａ ＋ ｌ ｂの同期ずれを
判定する補正判定回路、２１はこの同期ずれを補正する
補正回路、２２は検出値を取り込むマイクロプロセッサ
である。 □・
つぎに動作を説明する。 １］
パルス発振器５に周波数２ｎ’・ｆ （２ｎは位相角３
６０゜の分割数、ｆはレゾルバ励振周波数）のパルス信
号６を発生させ、分周器７により１／２ｎに分周すると
、周波数ｆの励振パルス８が得られる。この励振パルス
８を増幅器９で増幅した励振信号４によりレゾルバ移相
機１ａ、ｌｂを励振する。Reference numeral 20 denotes a correction determination circuit for determining the synchronization deviation of the resolver phase shifter 1a+lb, 21 a correction circuit for correcting this synchronization deviation, and 22 a microprocessor for taking in the detected value. □・ Next, the operation will be explained. 1] The pulse oscillator 5 has a frequency of 2n'・f (2n is a phase angle of 3
When a pulse signal 6 with a division number of 60 degrees (f is the resolver excitation frequency) is generated and divided into 1/2n by a frequency divider 7, an excitation pulse 8 with a frequency f is obtained. An excitation signal 4 obtained by amplifying this excitation pulse 8 by an amplifier 9 excites the resolver phase shifters 1a and lb.
レゾルバ移相機１の動作は第２図に示すように、レゾル
バの１次側にＢ＝Ｅｓｉｎωｔの電圧を加える１（、Ｅ
ｓ１ｎ２θの電圧が誘導する（ただし、θはレゾルバ軸
の回転角、ｋｌは比例定数）。このＥｓ、とＥｓ２とを
抵抗Ｒ１静電容量Ｃ、インダクタンスＬｋ、Ｍｈ（ｚθ
−７）（ただし、ｋ２は比例定数）が導かれる。すなわ
ち、レゾルバ移相機１の入力官と出力自。の位相は、第
３図に示すように、レゾルバ軸の回転角θに比例して変
位する。As shown in Fig. 2, the operation of the resolver phase shifter 1 is as follows: 1(, E
A voltage of s1n2θ is induced (where θ is the rotation angle of the resolver shaft, and kl is a proportionality constant). These Es and Es2 are connected by resistor R1 capacitance C, inductance Lk, Mh(zθ
-7) (where k2 is a proportionality constant) is derived. That is, the input and output of the resolver phase shifter 1. As shown in FIG. 3, the phase of is displaced in proportion to the rotation angle θ of the resolver shaft.
つぎに、レゾルバ移相ｍｌａ、ｌｂの移相信号１１ａ、
Ｉｌｂを増幅器１２ａ、１２ｂによりそれぞれ増幅し、
シュミット回路１４ａ、１４ｂによりそれぞれ矩形波に
整形する。そして、この矩形波の立上がシを微分回路１
７ａ、１７ｂにより微分パルス１６ａ、１６ｂに変換す
る。また、２進カウンタ１８ＫＦｉ前記パルス発振器５
からのパルス信号６を常時与えてカウントさせ、このカ
ウントの内容２°〜２ｎ−１ビツトを前記微分パルス１
６ａｌ１６ｂによりそれぞれの記憶回路１９ａ、１９ｂ
に記憶する。この記憶回路の内容は１／ｆの周期で更新
され、ｎビットのデジタル量として出力される。第３図
に各部の信号波形を示す。Next, resolver phase shift mla, phase shift signal 11a of lb,
Ilb is amplified by amplifiers 12a and 12b, respectively,
The signals are each shaped into a rectangular wave by Schmitt circuits 14a and 14b. Then, the rise of this rectangular wave causes the difference circuit 1
7a, 17b into differential pulses 16a, 16b. Moreover, the binary counter 18KFi said pulse oscillator 5
The pulse signal 6 from
6al16b, each memory circuit 19a, 19b
to be memorized. The contents of this memory circuit are updated at a cycle of 1/f and output as an n-bit digital quantity. Figure 3 shows signal waveforms at each part.
また、位置検出の範囲を広げる手段として、レゾルバ移
相機１ａ、ｌｂの入力軸を適当な伝達比（ここでハ１／
２°−３の場合で説明する）で回転伝達機構２により結
合しているため、上位のレゾルバ移相機１ａの検出値は
、上位の２′？″４桁〜を桁と上下位間の同期ずれ補正
のための冗長桁の２ｒ′−”桁〜２°−Ｓ桁とを示し、
下位のレゾルバ移相機１ｂの検出値は下位の２ 桁〜２
°桁を示す。In addition, as a means to widen the range of position detection, the input shafts of the resolver phase shifters 1a and lb can be adjusted to an appropriate transmission ratio (here,
(explained in the case of 2°-3)), the detected value of the upper resolver phase shifter 1a is 2'? ``4 digits ~'' indicates digits and 2r'-'' digits ~ 2°-S digits of redundant digits for correcting synchronization difference between upper and lower,
The detection value of the lower resolver phase shifter 1b is the lower two digits ~ 2
° Indicates digit.
回転伝達機構２には機械的あそび等があるため。This is because the rotation transmission mechanism 2 has mechanical play.
下位の検出値からの桁上げと、上位の検出値の変化が一
致しな゛い場合があシ、これを判定するために、補正判
定回路２０は上位の冗長桁の２ｎ−１桁〜２ｎ−３桁か
ら下位の２°−１桁〜２°−３桁を減じ、その差が１０
進法で５以上の場合、補正回路２１によシ上位の２２１
−４桁〜を桁に１を加え、差が一５以下の場合、補正回
路２１により上位の２２１−４桁〜２ｎ桁から１を減す
る。また、上記差の絶対値が４以下の場合は下位の２ｎ
−１桁〜を桁から上位２２ｎ−４桁〜を桁への桁上げが
起こらないので同期ずれの補正は行なわない。There may be cases where the carry from the lower detected value does not match the change in the upper detected value. - Subtract the lower 2°-1 digit to 2°-3 digit from the 3rd digit, and the difference is 10
If the value is 5 or more in base, the correction circuit 21 selects the upper 221
-4 digits to digits are incremented by 1, and if the difference is less than 15, the correction circuit 21 subtracts 1 from the upper 221-4 digits to 2n digits. In addition, if the absolute value of the above difference is 4 or less, the lower 2n
Since no carry occurs from the -1st digit to the upper 22n-4th digit, the synchronization shift is not corrected.
このようにして、マイクロプロセッサ２２に２ｎ −３
ビツトの検出値を取り込むことにより車輪の回転角度の
検出ができ、移動機械の基準点からの絶対位置検出がな
される。In this way, the microprocessor 22 has 2n −3
By taking in the detection value of the bit, the rotation angle of the wheel can be detected, and the absolute position of the mobile machine from the reference point can be detected.
以上述べたように、従来の絶対位置検出装置は、それぞ
れのレゾルバ移相機に対応して増幅器、シュミット回路
、微分回路および記憶回路をそれぞれ備え、また、レゾ
ルバ移相機間の同期ずれを補正する補正回路を備えてい
るため、レゾルバ移相機が増すごとに構成が複雑になり
、信頼性が低下し、装置が大型になり、また、補正の手
段を容易に変更できない等の欠点があった。As described above, the conventional absolute position detection device is equipped with an amplifier, a Schmitt circuit, a differentiation circuit, and a memory circuit corresponding to each resolver phase shifter, and also has a correction function for correcting synchronization deviation between the resolver phase shifters. As the number of resolver phase shifters increases, the structure becomes more complicated, the reliability decreases, the device becomes larger, and the correction means cannot be changed easily.
この発明は、このような従来の欠点に着目してなされた
ものであり、レゾルバ移相機からの移相信号を任意に選
択する選択回路を設け、シュミット回路、微分回路およ
び記憶回路を共用し、かつ、レゾルバ移相様間の同期ず
れの補正をマイクロプロセッサで処理することにより、
上記欠点を解決することを目的としている。The present invention has been made by focusing on such conventional drawbacks, and includes a selection circuit that arbitrarily selects a phase shift signal from a resolver phase shifter, and shares a Schmitt circuit, a differentiation circuit, and a memory circuit. In addition, by processing the correction of synchronization deviation between resolver phase shift patterns using a microprocessor,
The purpose is to solve the above drawbacks.
以下、この発明の一実施例を第４図、第５図に基づいて
説明する。なお、従来と同じものは同一符号をもって説
明を省略する。An embodiment of the present invention will be described below with reference to FIGS. 4 and 5. Components that are the same as those of the prior art are designated by the same reference numerals, and a description thereof will be omitted.
第４図において、２３はレゾルバ移相機１ａ。In FIG. 4, 23 is a resolver phase shifter 1a.
１ｂの移相信号１１ａ、１１ｂを任意に選択する選択回
路で、選択信号２４により前記移相信号１１ａ、１１ｂ
を増幅した増幅信号１３ａ、１３ｂを選択し、シュミッ
ト回路１４へ入力する。２２はこの選択回路２３に選択
信号２４を与え、また、励振信号８を入力して記憶回路
１９の内容を取り込み、同期ずれの補正をするマイクロ
プロセッサである。A selection circuit that arbitrarily selects the phase-shifted signals 11a and 11b of 1b.
The amplified signals 13a and 13b are selected and input to the Schmitt circuit 14. 22 is a microprocessor which supplies the selection signal 24 to the selection circuit 23, inputs the excitation signal 8, takes in the contents of the storage circuit 19, and corrects synchronization deviations.
つぎに動作を説明する。Next, the operation will be explained.
前記従来例と同様に、レゾルノ（移相機１ａ、１ｂの移
相信号１１ａ、ｌｌｂを増幅器１２ａ、１２ｂによりそ
れぞれ増幅する。この増幅信号１３ａ。Similar to the conventional example, the phase-shifted signals 11a and llb of the resorno phase shifters 1a and 1b are amplified by amplifiers 12a and 12b, respectively.This amplified signal 13a.
１３ｂを選択回路２３に入力すると、マイクロッ。13b is input to the selection circuit 23, the micro.
ロセツサ２２はこの選択回路２３を選択信号２４によっ
て制御し、最初に上位のレゾルノ（移相＋！ｋｔａから
の移相信号１１ａを選択する。以後、つき゛の（１）〜
（４）の動作を行なう。The processor 22 controls this selection circuit 23 using the selection signal 24, and first selects the phase shift signal 11a from the upper resolno (phase shift +!kta).
Perform operation (4).
（１）上記選択された増幅信号１３をシュミット回路１
４により矩形信号１５に変換する。(1) The above-selected amplified signal 13 is transferred to the Schmitt circuit 1
4 into a rectangular signal 15.
（２） この矩形信号の立上がりを微分回路１７によ
り微分パルス１６に変換する。(2) The rising edge of this rectangular signal is converted into a differentiated pulse 16 by the differentiating circuit 17.
（３）２進カウンタ１８にはノ（ルス信号６を常時与え
てカウントさせ、このカウントの内容２゜〜２ｎ−１ビ
ットを前記微分）くルス１６によりＢ己憶回路１９に記
憶する。(3) The binary counter 18 is constantly supplied with the pulse signal 6 to cause it to count, and the content of this count (2° to 2n-1 bits) is stored in the B memory circuit 19 by the differential pulse 16.
（４） マイクロプロセッサ２２ｔ’ｉ、励ａノ（ル
ス８のタイミングにより前記記憶回路１９の内容を取り
込む。 、
ここで、上述の、マイクロプロセッサ２２力；励振パル
ス８のタイミングにより記憶回路１９の内容を取り込む
過程を詳しく説明する。第５図に示すように、時刻Ｔに
おいてマイクロプロセッサ２２が増幅信号１３ａから増
幅信号１３ｂに選択を切換えたとする。この時、シュミ
ット回路１４からの矩形信号１５は第５図（ｄｌに示す
ようになり、時刻Ｔにおけるこの矩形信号１５の立上が
シ２５は増幅信号１３ｂの立上がり２６とは異なるため
、この立上がり２５により検出される位相差は正確では
ない。そこで、マイクロプロセッサ２２が正確な検出値
を取り込むためには、前記矩形信号１５のつぎの立上が
り２７により検出される位相差を取り込む必要があり、
そのため、マイクロプロセッサ２２は増幅信号１３ｂを
選択した後の励振パルス８の２回の立上がり２８．２９
を確認してから記憶回路１９の内容を取シ込む。(4) The microprocessor 22t'i reads the contents of the storage circuit 19 according to the timing of the excitation pulse 8. Here, the contents of the storage circuit 19 are taken in by the timing of the excitation pulse 8. As shown in FIG. 5, it is assumed that the microprocessor 22 switches the selection from the amplified signal 13a to the amplified signal 13b at time T. At this time, the rectangular signal 15 from the Schmitt circuit 14 is As shown in FIG. 5 (dl), the rising edge 25 of this rectangular signal 15 at time T is different from the rising edge 26 of the amplified signal 13b, so the phase difference detected by this rising edge 25 is not accurate. In order for the microprocessor 22 to capture an accurate detected value, it is necessary to capture the phase difference detected at the next rising edge 27 of the rectangular signal 15.
Therefore, the microprocessor 22 detects two rising edges 28 and 29 of the excitation pulse 8 after selecting the amplified signal 13b.
After confirming this, the contents of the memory circuit 19 are input.
つぎに、マイクロプロセッサ２２が再度選択回路２３を
制御し、下位のレゾルバ移相機１ｂの増幅信号１３ｂを
選択する。以後、上記ｔｌ）〜（４）の動作を行なう。Next, the microprocessor 22 controls the selection circuit 23 again to select the amplified signal 13b of the lower resolver phase shifter 1b. Thereafter, the operations tl) to (4) above are performed.
そして、マイクロプロセッサ２２Ｆｉ、上下位のレゾル
バ移相機１ａ、ｌｂからの位相差を取り込んだ後、同期
ずれの補正を処理し、２ｎ−３ビツトのデジタル量を検
出値として増９込む。Then, after taking in the phase difference from the microprocessor 22Fi and the upper and lower resolver phase shifters 1a and lb, correction of synchronization deviation is processed, and a digital amount of 2n-3 bits is increased as a detected value.
この検出値により車輪の回転角度が検出でき、移動機械
の基準点からの絶対位置検出がなされる。The rotation angle of the wheel can be detected from this detected value, and the absolute position of the mobile machine from the reference point can be detected.
以上説明したように、この発明によれば、レゾルバ移相
機からの移相信号を任意に選択する選択回路を設け、シ
ュミット回路、微分回路および記憶回路を共用し、レゾ
ルバ移相横開の同期ずれの補正をマイクロプロセッサの
内部で処理するようにしたため、レゾルバ移相機が増加
しても、構成が複雑にならず、回路の信頼性が向上し、
小型で安価な装置が提供でき、しかも、レゾルノく移相
様間の同期ずれの補正手段の変更が容易にできるので極
めて有用な効果がある。As explained above, according to the present invention, a selection circuit that arbitrarily selects a phase shift signal from a resolver phase shifter is provided, a Schmitt circuit, a differentiation circuit, and a memory circuit are shared, and the synchronization deviation of the resolver phase shift lateral opening is Since the correction is processed inside the microprocessor, even if the number of resolver phase shifters increases, the configuration does not become complicated, and the reliability of the circuit is improved.
A small and inexpensive device can be provided, and the means for correcting the synchronization deviation between resolono phase shift modes can be easily changed, which is extremely useful.
第１図は従来の絶対位置検出装置の制御装置のブロック
図、第２図はレゾル／＜移相機の回路図、第３図はレゾ
ルバ移相機の励振信号、移相信号の位相の関係を示した
特性図、第４図はこの発明の一実施例の制御装置のブロ
ック図、第５図はマイクロプロセッサが記憶回路の内容
を取り込むタイミンクを示した特性図である。
ｌａ、ｌｌ）・・・・・・レゾルバ移相機２・・・・・
・・・・回転伝達機構
３・・・・・・・・・励振回路
４・・・・・・・・・励振信号
５・・・・・・・・・パルス発振器
６・・・・・・・・・パルス信号
７・・・・・・・・・分周器
９・・・・・・・・・増幅器
１０・・・・・・位相差検出回路
１１ａ、ｆｉｂ・・・・・・移相信号
１２ａ、１２ｂ・・・・・・増幅器
１４ａ、１４ｂ・・・・・・シュミット回路１７ａ、１
７ｂ・・・・・・微分回路
１８・・・・・・２進カウンタ
１９ａ、１９ｂ・・・・・・記憶回路
２１・・・・・・補正回路
２２・・・・・・マイクロプロセッサ
２３・・・・・・選択回路
２４・・・・・・選択信号
なお、図中同一符号は、同一、または相当部分を示す。
代理人 葛野信−（ほか１名）
特許庁長官殿
ｌ ・ＩＧ ｆ’ｌ−の表示 特願昭５７−８’
１５６０号２、 ５１明の名称
絶対位置検出製電
、３ 補正をするｈ
事件との関係 特許出願人
住 所 東京都千代［Ｂ置火の内二丁目２番３
号名 称（６０１） 三菱電機株式会社代表者片由
仁八部
４代理人
５、補正の対象
（１）明細書の発明の詳細な説明の欄
（２）図面（第１図、第２図、第３図）６、補正の内容
（１）明細書の発明の詳細な説明の欄を次のように訂正
する。
ピ）第４頁第８行の「、インダクタンスＬ」を削除する
。
（ハ）第５頁第１行〜２行の「このカウントの」を「こ
の２進カウンタ１８の１と訂正する。
に）第５頁第４行の「この記憶回路の内容は１／／の」
を「この記憶回路の内容が各々レゾルバ移相機１ａ、ｌ
ｂの検出値であり、１／ｆの」と訂正する。
（ホ）第５頁第１１行〜１４行の［検出値は、・−・・
・・・・・を示す。］を「上記検出値は、上位の２桁〜
２Ｂ桁を示し、下位のレゾルバ移相機１ｂの上記検出値
は下位の２ｒ１１桁〜１桁を示す。また、上位の２ｎ″
桁〜２″−１桁は、上下位間の同期ずれ補正のための冗
長桁を示す。」と訂正する。
（へ）第５頁第坊行の「上位」を「下位」と訂正する。
（ト）第５頁第１９行の「下位」を「上位」と訂正する
。
ｉ２）図面を次のように訂正する。
図面第１図、第２図、第３図を添付別紙図面のとおり訂
正する。Fig. 1 is a block diagram of a control device for a conventional absolute position detection device, Fig. 2 is a circuit diagram of a resolver/< phase shifter, and Fig. 3 shows the phase relationship between the excitation signal and phase shift signal of the resolver phase shifter. FIG. 4 is a block diagram of a control device according to an embodiment of the present invention, and FIG. 5 is a characteristic diagram showing the timing at which the microprocessor takes in the contents of the memory circuit. la, ll)...Resolver phase shifter 2...
...Rotation transmission mechanism 3...Excitation circuit 4...Excitation signal 5...Pulse oscillator 6... . . . Pulse signal 7 . . . Frequency divider 9 . . . Amplifier 10 . . . Phase difference detection circuit 11a, fib . . . Phase signals 12a, 12b...Amplifiers 14a, 14b...Schmitt circuits 17a, 1
7b... Differentiation circuit 18... Binary counters 19a, 19b... Memory circuit 21... Correction circuit 22... Microprocessor 23. . . . Selection circuit 24 . . . Selection signal Note that the same reference numerals in the drawings indicate the same or equivalent parts. Agent Makoto Kuzuno (and 1 other person) Director General of the Japan Patent Office ・IG f'l- Display Patent application 1982-8'
1560 No. 2, 51 Akira's name Absolute Position Detection Electrical Manufacturing Co., Ltd., 3 Amend h Relationship with the case Patent applicant address Chiyo, Tokyo [2-2-3 B Okihi-no-uchi]
Title (601) Mitsubishi Electric Corporation Representative Katayuni 8th Department 4 Agent 5 Subject of amendment (1) Detailed description of the invention in the specification (2) Drawings (Fig. 1, Fig. 2, (Figure 3) 6. Contents of the amendment (1) The detailed description of the invention column in the specification is corrected as follows. B) Delete "Inductance L" in the 8th line of page 4. (C) Correct “this count” in lines 1 and 2 of page 5 to “1 of this binary counter 18.” B) “The contents of this memory circuit are 1//” in line 4 of page 5. of"
"The contents of this memory circuit are the resolver phase shifters 1a and 1, respectively.
It is the detected value of b, which is corrected as 1/f. (E) Page 5, lines 11 to 14 [Detected values are...
...indicates... ] to “The above detected value is the upper two digits ~
The detection value of the lower resolver phase shifter 1b indicates the lower 2r11 digit to 1 digit. Also, the top 2n″
The digits ~2''-1 indicate redundant digits for correcting the synchronization difference between the upper and lower parts.'' (To) Correct "upper" in the 5th page to "lower". (G) Correct "lower" in line 19 of page 5 to "higher." i2) Correct the drawing as follows. Figures 1, 2, and 3 of the drawings are corrected as shown in the attached attached drawings.
Claims (1)
複数のレゾルバ移相機と、パルス発振器。 分局器および増幅器からなり、このレゾルバ移相機に励
振信号を与える励振回路と、前記レゾルバ移相機それぞ
れに対応して設けられた、増幅器、シュミット回路、微
分回路、記憶回路および前記パルス発振器のパルス信号
によりカウントする２進カウ／りからなる位相差検出回
路と、前記レゾルバ移相機間の同期ずれを補正する補正
回路と、検出値を取り込むマイクロプロセッサとを備え
た絶対位置検出装置において、前記レゾルバ移相機から
の移相信号を任意に選択する選択回路を設けることによ
り前記シュミット回路、微分回路および記憶回路を共用
し、かつ、レゾルバ移相機間の同期ずれの補正を前記マ
イクロプロセッサで処理することを特徴とする絶対位置
検出装置。[Scope of Claims] A plurality of resolver phase shifters whose input shafts are coupled at an appropriate transmission ratio by a rotation transmission mechanism, and a pulse oscillator. An excitation circuit consisting of a branching unit and an amplifier and giving an excitation signal to the resolver phase shifter, an amplifier, a Schmitt circuit, a differentiating circuit, a memory circuit and a pulse signal of the pulse oscillator provided corresponding to each of the resolver phase shifters. In the absolute position detection device, the absolute position detection device is equipped with a phase difference detection circuit consisting of a binary counter that counts according to By providing a selection circuit that arbitrarily selects the phase shift signal from the phase shifter, the Schmitt circuit, the differentiation circuit, and the memory circuit can be shared, and the correction of synchronization between the resolver and phase shifter can be processed by the microprocessor. Features: Absolute position detection device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8756082A JPS58204311A (en) | 1982-05-24 | 1982-05-24 | Detector for absolute position |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8756082A JPS58204311A (en) | 1982-05-24 | 1982-05-24 | Detector for absolute position |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58204311A true JPS58204311A (en) | 1983-11-29 |
| JPH0134327B2 JPH0134327B2 (en) | 1989-07-19 |
Family
ID=13918369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8756082A Granted JPS58204311A (en) | 1982-05-24 | 1982-05-24 | Detector for absolute position |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58204311A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1984004162A1 (en) * | 1983-04-11 | 1984-10-25 | Fanuc Ltd | Method of detecting absolute position of servo control system |
| WO1984004161A1 (en) * | 1983-04-11 | 1984-10-25 | Fanuc Ltd | Method of detecting absolute position of servo control system |
| WO1984004587A1 (en) * | 1983-05-09 | 1984-11-22 | Fanuc Ltd | Absolute value detection apparatus for detecting rotational position |
| JPS60162918A (en) * | 1984-02-03 | 1985-08-24 | Fuji Kikai Seizo Kk | Multiple rotation absolute detector |
| JPH0779589A (en) * | 1993-09-09 | 1995-03-20 | Ckd Corp | Motor controller |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4984673A (en) * | 1972-12-20 | 1974-08-14 | ||
| JPS56116196A (en) * | 1980-02-20 | 1981-09-11 | Mitsubishi Electric Corp | Step comparator for position detector |
-
1982
- 1982-05-24 JP JP8756082A patent/JPS58204311A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4984673A (en) * | 1972-12-20 | 1974-08-14 | ||
| JPS56116196A (en) * | 1980-02-20 | 1981-09-11 | Mitsubishi Electric Corp | Step comparator for position detector |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1984004162A1 (en) * | 1983-04-11 | 1984-10-25 | Fanuc Ltd | Method of detecting absolute position of servo control system |
| WO1984004161A1 (en) * | 1983-04-11 | 1984-10-25 | Fanuc Ltd | Method of detecting absolute position of servo control system |
| WO1984004587A1 (en) * | 1983-05-09 | 1984-11-22 | Fanuc Ltd | Absolute value detection apparatus for detecting rotational position |
| JPS60162918A (en) * | 1984-02-03 | 1985-08-24 | Fuji Kikai Seizo Kk | Multiple rotation absolute detector |
| JPH0542601B2 (en) * | 1984-02-03 | 1993-06-29 | Fuji Machine Mfg | |
| JPH0779589A (en) * | 1993-09-09 | 1995-03-20 | Ckd Corp | Motor controller |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0134327B2 (en) | 1989-07-19 |
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