JPS58202546A - Formation of element isolation film - Google Patents
Formation of element isolation filmInfo
- Publication number
- JPS58202546A JPS58202546A JP8744182A JP8744182A JPS58202546A JP S58202546 A JPS58202546 A JP S58202546A JP 8744182 A JP8744182 A JP 8744182A JP 8744182 A JP8744182 A JP 8744182A JP S58202546 A JPS58202546 A JP S58202546A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- etching
- recess
- element isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、シリコン基板に形成された半導体素子間を
分離する素子間分離膜の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming an inter-element isolation film that isolates semiconductor elements formed on a silicon substrate.
従来このような素子間分離膜の形成方法としては、いわ
ゆる選択酸化法が一般に用いられている。Conventionally, a so-called selective oxidation method is generally used as a method for forming such an element isolation film.
この方法は、例えば第1図(a) K示すように、シリ
コン基板0υの表面に薄い熱酸化膜QりとCVD窒化膜
a3を設けて熱酸化を行なうものである。CVD窒化膜
α〜は、耐酸化性が強いためにこの下の部分は酸化され
ず、露出した部分にのみ同図(b)に示すように厚い酸
化膜aaが珍成される。In this method, for example, as shown in FIG. 1(a) K, a thin thermal oxide film Q and a CVD nitride film a3 are provided on the surface of a silicon substrate 0υ, and then thermal oxidation is performed. Since the CVD nitride film α~ has strong oxidation resistance, the lower part is not oxidized, and a thick oxide film aa is formed only on the exposed part as shown in FIG.
しかしながら、この方法では、バーズ・ヘッド(btr
as head) (19およびバーズ・ピーク(bi
rd;beak)叫と呼ばれる部分が不可避的に形成さ
れ、電極配線の断線や素子の高密度化を妨げる大きな要
因となっていた。However, with this method, bird's head (btr
as head) (19 and Birds Peak (bi
rd;beak) portions are unavoidably formed, which is a major factor that prevents disconnection of electrode wiring and higher density of elements.
この発明は、このような状況に鑑みてなされたものであ
シ、その目的は、バーズ・ピーク、バーズ・ヘッドの生
じない素子間分離膜の形成方法を提供することにある。The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for forming an isolation film between elements in which bird's peaks and bird's heads do not occur.
このような目的を達成するために、この発明は、シリコ
ン基板に選択エツチングによシ凹部を形成し、シリコン
酸化膜を堆積した後、異方性エツチングに□よシ上記酸
化膜の四部の縁部を前記選択エツチングに用いたマスク
の端部が露出するまで除去して傾斜面を形成し、その後
上記選択エツチングに用いたマスクをその上のシリコン
酸化膜と共に除去するものである。以下、実施例を用い
てこの発明の詳細な説明する。In order to achieve such an object, the present invention forms recesses in a silicon substrate by selective etching, deposits a silicon oxide film, and then anisotropically etches the edges of the four parts of the oxide film. The mask used in the selective etching is removed until the end of the mask is exposed to form an inclined surface, and then the mask used in the selective etching is removed together with the silicon oxide film thereon. The present invention will be described in detail below using examples.
第2図(a)〜優)はこの発明の一実施例における各工
程を示す断面図である。FIGS. 2(a) to 2(a) are sectional views showing each step in an embodiment of the present invention.
先ず、シリコン基板Qυの上にアルミニウム膜(2)を
形成し、これをそ゛の上に形成したレジスト膜(ハ)を
パターニングマスクとしてエツチングし、素子間盆離用
酸化膜形成部位1/c如応する部分を除去して開孔r;
!4を形成する。エツチング法としては、ウェットある
いはドライのいずれでも曳い(第2図(a))。First, an aluminum film (2) is formed on a silicon substrate Qυ, and a resist film (c) formed thereon is etched as a patterning mask to form an oxide film forming region 1/c for isolation between elements. Remove the corresponding part to open a hole r;
! form 4. The etching method can be wet or dry (Figure 2(a)).
次いで、上記アルミニウム族(23およびレジスト膜(
ハ)をマスクとして、フレオン系のガスエツチングによ
シリコン基板Qυに凹部(ハ)を形成する。この場合の
エツチングは、等方性でも良い(第2図(b) ) 0
次に、上記凹部(251の部分のシリコン基板Qυに、
イオン注入法によシネ細物(ハ)を注入する。これはこ
の素子間分離領域において表面反転が起こるのを防止す
るためである(第2図(C))。Next, the aluminum group (23) and the resist film (
Using c) as a mask, a recess (c) is formed in the silicon substrate Qυ by Freon gas etching. In this case, the etching may be isotropic (FIG. 2(b)).
Inject the cine particles (c) by ion implantation. This is to prevent surface inversion from occurring in this element isolation region (FIG. 2(C)).
次いで、レジスト族(2階を除去した後、上記凹部(ハ
)を含めシリコン基板t2Bの表面全体に、減圧もしく
は常圧CVD法によシ酸化膜(2)を形成する。この場
合、凹部(ハ)を形成する際にエツチングマスクとして
用いたアルミニウム膜Q)はそのままであるから、上記
酸化膜(5)は凹部(ハ)の部分を除き、アルミニウム
膜@の上に堆積する(第2図(d))。Next, after removing the resist group (second layer), a silicon oxide film (2) is formed on the entire surface of the silicon substrate t2B, including the recesses (c), by low pressure or atmospheric pressure CVD. Since the aluminum film Q) used as an etching mask when forming the etching mask C) remains as it is, the oxide film Q) is deposited on the aluminum film @ except for the recessed portions (C) (see Fig. 2). (d)).
次に、マスクを用いず、′上記酸化膜(5)の全面に異
方性エツチングを施す。エツチング速度がイオンの衝突
する角度に依存し、凹部(至)の縁の段差部で大きくな
ることから、そこに傾斜面(ハ)が形成される。このエ
ツチングは、アルミニウム族(5)の端部が傾斜面(ハ
)に表われるまで行なう(第2図(e))。Next, without using a mask, anisotropic etching is applied to the entire surface of the oxide film (5). Since the etching rate depends on the angle at which the ions collide and increases at the stepped portion at the edge of the recess, an inclined surface (c) is formed there. This etching is continued until the end of the aluminum group (5) appears on the inclined surface (c) (FIG. 2(e)).
そこで、この傾斜面(281を利用し、下敷となってい
る前記アルミニウム膜(2)を除去すれに1その上の酸
化膜Q7)はレジスト膜(ハ)と共にリフト・オフによ
シ除去され、凹部に)の内部の酸化膜−のみが残される
(第2図(f) )、。Therefore, using this inclined surface (281), in order to remove the underlying aluminum film (2), the oxide film Q7 thereon is removed by lift-off together with the resist film (c). Only the oxide film inside the recess (Fig. 2(f)) remains.
引続き熱処理を行なうことによシ、不純物(至)を活性
化すると共に、上記酸化膜(ロ)の形状をなだらかにす
る。ヒの熱処理によシ、酸化膜(2)は焼きしめられ、
その欠陥密度を減少させることができる(第2図(g)
)。By subsequently performing heat treatment, the impurities (2) are activated and the shape of the oxide film (2) is made smooth. After the heat treatment, the oxide film (2) is hardened,
The defect density can be reduced (Fig. 2 (g)
).
こうして形成された酸化膜■を素子間分離膜として用い
れば、バーズ拳ビーク、バーズ・ヘッドのない理想的な
形状の素子間分離膜が得られる。If the thus formed oxide film (1) is used as an inter-element isolation film, an ideal-shaped inter-element isolation film without a bird's fist beak or bird's head can be obtained.
なお、上述した実施例においては、シリコン基板に選択
エツチングによ)凹部を形成する際のエツチングマスク
としてアルミニウム膜を用いた。In the above-mentioned embodiment, an aluminum film was used as an etching mask when forming a recess (by selective etching) on a silicon substrate.
これは、レジスト等を用いた場合に比較してシャープな
パターン形成が可能であること、および後のり7ト・オ
フ工程において剥離し易いという利点を有するためであ
るが、必ずしもアルミニウム膜を用いる必要はなく、一
般のレジスト膜でも、 、また例えにポリイミド樹脂膜
等を用いても良い。This is because it has the advantage of being able to form sharper patterns than when using resist, etc., and that it is easier to peel off in the subsequent post-off process, but it is not always necessary to use an aluminum film. Instead, a general resist film or, for example, a polyimide resin film may be used.
また、シリコン酸化膜を堆積する方法としては、CVD
法に限らず、例えばスパッタリング法等を用いても良い
。In addition, as a method of depositing a silicon oxide film, CVD
For example, a sputtering method or the like may be used.
以上説明したように1この発明によれば、バーズ・ピー
ク、バーズ・ヘッドのない理想的な形状に防ぐことがで
きると共に、素子間分離領域が小さくでき、素子の集積
度を上げることができるという効果を有する。As explained above, 1. According to the present invention, it is possible to prevent an ideal shape without bird's peaks and bird's heads, and also to reduce the isolation region between elements and increase the degree of integration of elements. have an effect.
第1図(a)、 、 (b)は従来の素子間分離膜の形
成方法を示す断面図、第2図(a)〜ωはこの発明の一
実施例における各工程を示す断面図である。
Qυ・・・・シリコン基板、■・・・・アルミニウム膜
、(ハ)・・・・レジスト膜、(ハ)・・・・凹部、Q
η・・・・酸化膜、(ハ)・・・・傾斜面。
代理人 葛 野 信 −(外1名)FIGS. 1(a), 1(b) are cross-sectional views showing a conventional method for forming an isolation film between elements, and FIGS. 2(a) to ω are cross-sectional views showing each step in an embodiment of the present invention. . Qυ...Silicon substrate, ■...Aluminum film, (C)...Resist film, (C)...Concavity, Q
η...Oxide film, (c)...Slanted surface. Agent Shin Kuzuno - (1 other person)
Claims (1)
分離膜の形成方法において、シリコン基板上にパターン
形成用のエツチングマスクを形成する工程と、このエツ
チングマスクを介してシリコン基板にエツチングを施し
素子間分離用酸化膜の形成部位に凹部を形成する工程と
、との凹部を含むシリコン基板表面にシリコン酸化膜を
形成する工程と、このシリコン酸化膜に異方性エツチン
グを施し上記凹部の縁部を上記エツチングマスクの端部
が露出するまで除去して傾斜面を形成する工程と、上記
エツチングマスクをその上のシリコン酸化膜と共に除去
することを特徴とする素子間分離膜の形成方法。A method for forming an element isolation film that separates semiconductor elements formed on a silicon substrate includes a step of forming an etching mask for pattern formation on the silicon substrate, and etching the silicon substrate through this etching mask to separate the elements between the elements. a step of forming a recess in the region where the isolation oxide film is to be formed, a step of forming a silicon oxide film on the surface of the silicon substrate including the recess, and anisotropic etching of the silicon oxide film to remove the edges of the recess. A method for forming an inter-element isolation film, comprising the steps of: removing the etching mask until an end thereof is exposed to form an inclined surface; and removing the etching mask together with the silicon oxide film thereon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8744182A JPS58202546A (en) | 1982-05-21 | 1982-05-21 | Formation of element isolation film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8744182A JPS58202546A (en) | 1982-05-21 | 1982-05-21 | Formation of element isolation film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58202546A true JPS58202546A (en) | 1983-11-25 |
Family
ID=13914939
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8744182A Pending JPS58202546A (en) | 1982-05-21 | 1982-05-21 | Formation of element isolation film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58202546A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60187036A (en) * | 1984-03-07 | 1985-09-24 | Agency Of Ind Science & Technol | Manufacture of inter-element isolation region |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54591A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Element isolating method |
JPS542685A (en) * | 1977-06-08 | 1979-01-10 | Nec Corp | Forming method for metal wiring |
-
1982
- 1982-05-21 JP JP8744182A patent/JPS58202546A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54591A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Element isolating method |
JPS542685A (en) * | 1977-06-08 | 1979-01-10 | Nec Corp | Forming method for metal wiring |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60187036A (en) * | 1984-03-07 | 1985-09-24 | Agency Of Ind Science & Technol | Manufacture of inter-element isolation region |
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