JPS58202540A - Method of bonding fine positioning by stand-off - Google Patents

Method of bonding fine positioning by stand-off

Info

Publication number
JPS58202540A
JPS58202540A JP8611182A JP8611182A JPS58202540A JP S58202540 A JPS58202540 A JP S58202540A JP 8611182 A JP8611182 A JP 8611182A JP 8611182 A JP8611182 A JP 8611182A JP S58202540 A JPS58202540 A JP S58202540A
Authority
JP
Japan
Prior art keywords
stand
wiring board
solder
bumps
positioning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8611182A
Other languages
Japanese (ja)
Inventor
Yoshiaki Takeuchi
善明 竹内
Koichi Fujiwara
幸一 藤原
Shigeyuki Tsurumi
重行 鶴見
Isamu Odaka
勇 小高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP8611182A priority Critical patent/JPS58202540A/en
Publication of JPS58202540A publication Critical patent/JPS58202540A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the accuracy of positioning by a method weherin the positioning of connecting bumps is performed by utilizing the stand-off between an IC device and a wiring substrate. CONSTITUTION:When the IC device 1 and the wiring substrate 2 are connected by the bumps 5 of solder, etc. in a state of opposition, a plurality of recesses 7 are provided either on the device or on the substrate 2, and the stand-off 3 of a projection is provided at the position opposed to the recess 7 on the other. Then, since the projection 3 and the recess 7 are not fitted each other in the case of generation of slippage at the position of the bumps 5, difference generates to the gap between the device 1 and the substrate 2, and therefore the positional displacement can be judged by the measurement of this gap.

Description

【発明の詳細な説明】 本発明は半導体を初めとする集積回路の高密度実装方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for high-density packaging of integrated circuits including semiconductors.

従来より集積回路の高密度実装にはフリップチップボン
ディングが有効であるとされているが、さらに高密度化
するためには、はんだ等による接続バンプを微細化し、
接続密度を高める必要がある。そのためには位置合せ精
度の高度化が必要であり、従来の装置では高い信頼性は
得難い。また、フリップチップボンディングは接続バン
プが対向するフェイス・ダウン法であるため、接続後に
バンプ位置の゛整合性を確認することができないという
欠点があった。スタンド・オフは配線基板上に設けられ
た柱状の突起であシ、従来は例えば配線基板のデバイス
の四隅に対応する位置にスタンド・オフをはんだリフ口
温度よシも融点の高い材料を用いて蒸着することにより
、はんだリフロ時にデバイスと配線基板との間隔を制御
してはんだの流出やはんだバンプ相互の短絡を防止し、
リフロ後はその間隔をスタンド・オフの高さにょシ均一
化することを目的として用いられていた。Flip chip bonding has traditionally been considered effective for high-density mounting of integrated circuits, but in order to achieve even higher density, it is necessary to miniaturize the connection bumps using solder, etc.
Connection density needs to be increased. For this purpose, it is necessary to improve the alignment accuracy, and it is difficult to achieve high reliability with conventional devices. Furthermore, since flip-chip bonding is a face-down method in which connection bumps face each other, it has the disadvantage that it is not possible to confirm the consistency of bump positions after bonding. Standoffs are pillar-shaped protrusions provided on a wiring board. Conventionally, standoffs were placed at positions corresponding to the four corners of a device on a wiring board using a material with a higher melting point than the solder opening temperature. By vapor deposition, it is possible to control the distance between the device and the wiring board during solder reflow to prevent solder from flowing out and shorting between solder bumps.
After reflow, the purpose was to equalize the spacing to the standoff height.

また、従来の位置合せ法の場合、リフ口前のデバイスは
フラックスの粘着性のみにより配線基板上に保持してい
たため、リフロ工程への運搬中には振動、衝撃等が加わ
らないように取扱上の注意が必要であった。In addition, in the case of the conventional alignment method, the device in front of the reflow opening was held on the wiring board only by the adhesiveness of the flux, so care must be taken to prevent vibrations, shocks, etc. from being applied during transportation to the reflow process. Caution was required.

本発明は、これらの欠点を除去するため、スタンド・オ
フにより位置の整合をとり、位置ずれをデバイスと配線
基板の間隔の測定によシわかるようにしたスタンド・オ
フによるボンディング微細位置合せ方法を提供するもの
である。In order to eliminate these drawbacks, the present invention provides a bonding microalignment method using stand-offs, which aligns the positions using stand-offs and makes it possible to detect positional deviations by measuring the distance between the device and the wiring board. This is what we provide.

以下図面により本発明の詳細な説明する。The present invention will be explained in detail below with reference to the drawings.

第１図及び第２図は本発明の実施例であって、１は集積
回路デバイス基板、２は配線基板、３は凸部となるスタ
ンド・オフ、４は回路パターン及び絶縁膜、５は接続用
はんだバンク、６はバンプ用のポンディングパッド、７
は・スタンド・オフに１５、□ 対向しかん合するくほみ（四部゛）である。ｍ１図はス
タンド・オフ部の断面図である。スタンド・オフ３はデ
バイス１と配線基板２０間隔を規定するものであるが、
スタンド・オフ３の先端がくほみ７に納まれば、両側に
あるバンプ５の位置合せが行なえるように、デバイス１
上にくぼみ７を設けた。よって、バンプ５の位置にずれ
が生じている場合にはスタンド・オフ３とくぼみ７がか
ん合しないため、デバイス１と配線基板２の間隔に差が
生じ、この間隔（ｈ）の測定により位置ずれが判断出来
る。本実施例ではデバイス１．配線基板２としてＳｉ基
板を用い、スタンド・オフ３１回路パターン及び絶縁膜
４．はんだバンプ５．ポンディングパッド６はメタルマ
スクを用いて蒸着により形成した。それぞれの材料とし
て３−Ｐｄ（１００μｍ（＄）。1 and 2 show embodiments of the present invention, in which 1 is an integrated circuit device substrate, 2 is a wiring board, 3 is a standoff serving as a convex portion, 4 is a circuit pattern and an insulating film, and 5 is a connection. 6 is a solder bank for bumps, 7 is a bonding pad for bumps, and 7 is a solder bank for bumps.
The stand-off is 15, □ the opposite mating Kuhomi (four parts). Figure m1 is a sectional view of the standoff part. The standoff 3 defines the distance between the device 1 and the wiring board 20,
Once the tip of the standoff 3 is in the groove 7, move the device 1 so that the bumps 5 on both sides can be aligned.
A recess 7 was provided on the top. Therefore, if there is a deviation in the position of the bump 5, the standoff 3 and the recess 7 will not engage with each other, resulting in a difference in the distance between the device 1 and the wiring board 2, and the measurement of this distance (h) will determine the position. Discrepancies can be determined. In this embodiment, device 1. A Si substrate is used as the wiring board 2, and a standoff 31 circuit pattern and an insulating film 4. Solder bump5. The bonding pad 6 was formed by vapor deposition using a metal mask. 3-Pd (100 μm ($)) as each material.

２０μｍ（ｈ））、　４−８ｉＯ（４μｍ（ｈ）、　７
は１００μｍ（φ）、はんだ用の窓径は５０ｐｍ（１６
））、　５−Ｐｂ５ｎ　（６２：３８）（１００μｍ（
φ）、５／ｊｍ　　）　、６−Ｃｕ　（８０μｍ’φ）
、１μｍ）を用いた。デバイス１の大きさは２．７ｍＸ
２．７ｍとし、ボンティングパッド６は中心間距離を２
００μｍとして１辺当り１０個で計４０個設けた。〈は
み７はデバイス１の四隅に設けた。配線基板２０大きさ
は５　ｙ　Ｘ　５　ｍｓとしデバイス１と同じパターン
を蒸着してくぼみ７に対向する位置にスタンド・オフ３
を設けた。このボンディングにより精度約２μｍの位置
合せが達成できた。また、位置合せ装置の精度が２０μ
ｍ程度しかない場合にも、位置合せ後に配線基板に微小
振動を加えることにより上記精度の位置合せが可能とな
った。20 μm (h)), 4-8iO (4 μm (h), 7
is 100 μm (φ), and the window diameter for soldering is 50 pm (16
)), 5-Pb5n (62:38) (100 μm (
φ), 5/jm), 6-Cu (80μm'φ)
, 1 μm) was used. The size of device 1 is 2.7mX
2.7m, and the distance between the centers of the bonding pads 6 is 2.
00 μm, 10 pieces per side, 40 pieces in total were provided. <The scissors 7 were provided at the four corners of the device 1. The size of the wiring board 20 is 5 y x 5 ms, and the same pattern as the device 1 is deposited, and a standoff 3 is placed opposite the recess 7.
has been established. By this bonding, alignment with an accuracy of about 2 μm could be achieved. In addition, the accuracy of the alignment device is 20μ
Even when the distance is only about m, alignment with the above-mentioned accuracy is possible by applying minute vibrations to the wiring board after alignment.

第２図は上記のモデル試験で位置ずれが生じた場合のデ
バイス１と配線基板２の位置関係を示した図である。ｌ
ａｌが正常な場合で全部のスタンド・オフが対向の四部
とかん合しているので、基板間隔ｄ＝ｈ　（正常な基板
間隔）となっている。１ｂ）。FIG. 2 is a diagram showing the positional relationship between the device 1 and the wiring board 2 when a positional shift occurs in the above model test. l
When al is normal, all the standoffs are engaged with the four opposing parts, so the board spacing d=h (normal board spacing). 1b).

＋０１は位置ずれが生じた場合でｌｂｌは一方がｄ＞ｈ
。+01 is when a positional shift occurs, and lbl is one side when d>h
.

もう一方はｄ＝ｈで片方のみがかん合している場合、（
０）は両方ともずれが生じてｄ＞ｈとなっている場合の
図である。いずれの場合も基板間隔を測定することによ
り、バンプ位置の整合性が判断出来る。よって基板間隔
の測定後にはんだのりフロを行うことにより、位置ずれ
が原因となる導通不良、短絡等の不良発生を防ぐことが
できた。If the other one is d=h and only one is engaged, (
0) is a diagram when a deviation occurs in both cases and d>h. In either case, the consistency of the bump positions can be determined by measuring the substrate spacing. Therefore, by performing solder flow after measuring the substrate spacing, it was possible to prevent defects such as conduction defects and short circuits caused by positional deviations.

以上説明したように、本発明によれば、スタン５− ド・オフを利用して接続用バンプの位置合せができるの
で、（１）位置合せの精度が向上すること、（２）信頼
性が向上すること、（３）装置の精度を向上させる必要
がないこと、（４）位置の整合性がリフ日前に確認でき
ること、（５）位置合せ後の取扱いが容易であること等
の利点がある。As explained above, according to the present invention, since the connection bumps can be aligned using stand five-off, (1) alignment accuracy is improved, and (2) reliability is improved. (3) There is no need to improve the accuracy of the device, (4) The consistency of the position can be confirmed before the ref date, and (5) It is easy to handle after alignment. .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の対象となる接面の断面図、第２図は位
置ずれによるデバイスと配線基板の位置関係を示す正面
図である。 ｌ・・・集積回路デバイス、　２・・・配置１ＪＭ板、
３・・・スタンド・オフ（凸部）、　４・・・回路パタ
ーン及び絶縁膜、　　５・・・はんだバンプ、６・・・
ポンディングパッド、　　７・・・スタンド・オフに対
向するくぼみ（凹部）。 特許出願人　　日本電信電話公社 代　理　　人　　　白　　水　　常　　雄性１名 　６−FIG. 1 is a sectional view of a contact surface to which the present invention is applied, and FIG. 2 is a front view showing the positional relationship between a device and a wiring board due to positional deviation. l...Integrated circuit device, 2...Arrangement 1JM board,
3... Standoff (protrusion), 4... Circuit pattern and insulating film, 5... Solder bump, 6...
Ponting pad, 7... recess (concavity) facing the stand-off. Patent applicant: Nippon Telegraph and Telephone Public Corporation Representative: Tsune Hakumizu Male: 1 person 6-

Claims (1)

【特許請求の範囲】[Claims] 集積回路デバイスと配線基板を対面させた状態ではんだ
等のバンプにより接続する場合に、前記デバイス側と前
記配線基板のいずれか一方に複数の凹部を設け、他方に
は前記四部と対向する位置に該凹部にかん合する凸部を
設けることによ如、前記デバイスと前記配線基板の間隔
調節とりフロ時の前記はんだの流出と該はんだのバンプ
による配線相互間の短絡をさけるためのスタンド・オフ
の役割を持たせるとともに、前記凸部と前記凹部のかん
合により、高精度の位置合せならびに該位置合せ後の位
置の確認を容易処したことを特徴とするスタンド・オフ
によるボンディング微細位置合せ方法。When connecting an integrated circuit device and a wiring board with bumps such as solder while facing each other, a plurality of recesses are provided on either the device side or the wiring board, and the other side is provided with a plurality of recesses at positions facing the four parts. By providing a convex portion that engages with the concave portion, a stand-off is provided to adjust the distance between the device and the wiring board, and to prevent the solder from flowing out during flow and shorting between the wires due to solder bumps. A bonding fine positioning method using a stand-off, characterized in that the mating of the convex part and the concave part facilitates highly accurate positioning and confirmation of the position after the positioning. .
JP8611182A 1982-05-21 1982-05-21 Method of bonding fine positioning by stand-off Pending JPS58202540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8611182A JPS58202540A (en) 1982-05-21 1982-05-21 Method of bonding fine positioning by stand-off

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8611182A JPS58202540A (en) 1982-05-21 1982-05-21 Method of bonding fine positioning by stand-off

Publications (1)

Publication Number Publication Date
JPS58202540A true JPS58202540A (en) 1983-11-25

Family

ID=13877585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8611182A Pending JPS58202540A (en) 1982-05-21 1982-05-21 Method of bonding fine positioning by stand-off

Country Status (1)

Country Link
JP (1) JPS58202540A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6255996A (en) * 1985-09-05 1987-03-11 日本電気株式会社 Wiring board
JPS6411025U (en) * 1987-07-10 1989-01-20
US4818728A (en) * 1986-12-03 1989-04-04 Sharp Kabushiki Kaisha Method of making a hybrid semiconductor device
JPH0191320U (en) * 1987-12-09 1989-06-15
US4874721A (en) * 1985-11-11 1989-10-17 Nec Corporation Method of manufacturing a multichip package with increased adhesive strength
JPH06295937A (en) * 1993-03-26 1994-10-21 Nec Corp Mounting method of photoelectric element

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6255996A (en) * 1985-09-05 1987-03-11 日本電気株式会社 Wiring board
US4874721A (en) * 1985-11-11 1989-10-17 Nec Corporation Method of manufacturing a multichip package with increased adhesive strength
US4818728A (en) * 1986-12-03 1989-04-04 Sharp Kabushiki Kaisha Method of making a hybrid semiconductor device
JPS6411025U (en) * 1987-07-10 1989-01-20
JPH0191320U (en) * 1987-12-09 1989-06-15
JPH06295937A (en) * 1993-03-26 1994-10-21 Nec Corp Mounting method of photoelectric element

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