JPS5820018A - Agc circuit - Google Patents
Agc circuitInfo
- Publication number
- JPS5820018A JPS5820018A JP11968081A JP11968081A JPS5820018A JP S5820018 A JPS5820018 A JP S5820018A JP 11968081 A JP11968081 A JP 11968081A JP 11968081 A JP11968081 A JP 11968081A JP S5820018 A JPS5820018 A JP S5820018A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- switch
- agc
- time constant
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 abstract 1
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 101000995861 Arabidopsis thaliana Regulatory protein NPR1 Proteins 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、ＡＧＣＷ性の立上り時間を短縮したＡＧＣ
回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides an AGC with reduced rise time of AGCW property.
It is related to circuits.
一般のＡＧＣ回路ではその閉ループ中の単一の時定数回
路によってＡＧＣ応答特性が決定されている０したがっ
てその回路の時定数が短かすぎると、閉ループ中に、例
えば、ろ波器等のような遅延時間を有する素子が有る場
合に杜、位相余裕が少°なくなシ、そのループは発振す
る恐れがある０したがって、ＡＧＣ回路の立上シ時間の
短縮をはかるため、単に時定数を小さくとる手段はとり
にくかった０
本発明は、このような欠点を回避することを目る０
第１図は、本発明の一実施例を示すブロック図である。In a general AGC circuit, the AGC response characteristics are determined by a single time constant circuit in the closed loop. Therefore, if the time constant of that circuit is too short, the If there is an element with a delay time, the phase margin will be reduced and the loop may oscillate.Therefore, in order to shorten the start-up time of the AGC circuit, the time constant is simply set small. The present invention aims to avoid such drawbacks. FIG. 1 is a block diagram showing an embodiment of the present invention.
検波器ｌを被制御入力側に接続する。同検波器の出力側
に短および長時定数回路３，５を並列に接続し、両回踏
出力をＡＧＣ出力とするＯ検波器ｌと両回路３，５との
間に夫々スイッチ２゜４を挿入接続する。さらに検波器
６を前°記被制御入力に接続し、同出力、を直流増幅器
７の入力側に接続する。増幅器７の出力側を時定数切替
器８に接続し、時定数切替器８の出力をそれぞれ前記ス
イッチ２，４の制御入力側に接続する“。A detector l is connected to the controlled input side. Short and long time constant circuits 3 and 5 are connected in parallel to the output side of the detector, and switches 2° and 4 are connected between the O detector 1 and both circuits 3 and 5, which use the outputs of both circuits as AGC outputs. Insert and connect. Further, a wave detector 6 is connected to the controlled input, and its output is connected to the input side of the DC amplifier 7. The output side of the amplifier 7 is connected to a time constant switch 8, and the outputs of the time constant switch 8 are connected to the control input sides of the switches 2 and 4, respectively.
検波器１に被制御入力電圧が印加されると、検波器１の
出力には、入力電圧に比例した、直流電圧が発生し、こ
の直流電圧が同時に時定数回路３゜５に印加され、ＡＧ
Ｃ電圧出力となる。When a controlled input voltage is applied to the detector 1, a DC voltage proportional to the input voltage is generated at the output of the detector 1, and this DC voltage is simultaneously applied to the time constant circuit 3.
C voltage output.
これと同時に、検波器６によって、検波された被制御入
力電圧は、直流増幅器７に印加される。At the same time, the controlled input voltage detected by the wave detector 6 is applied to the DC amplifier 7.
この直流増幅器７はあ゛る一定のスレッシュホルド値ｖ
１以上の入力があったとき動作するように設定されてい
る。This DC amplifier 7 has a certain threshold value v
It is set to operate when there is one or more inputs.
入力電圧がこの値を超えると、時定数切替器８に増幅さ
れた電圧が印加され、スイッチ２，４のいずれかも接に
し他を断にし、時定数回路３，５の切替を行なう。When the input voltage exceeds this value, the amplified voltage is applied to the time constant switch 8, which closes one of the switches 2 and 4 and turns the other off, thereby switching the time constant circuits 3 and 5.
すなわち検波器６の出力電圧が直流増幅器７の所定の入
力レベルすなわちスジツシュホルド値ｖ１を超えた場合
、たとえばスイッチ２を接とし、比。That is, when the output voltage of the wave detector 6 exceeds the predetermined input level of the DC amplifier 7, that is, the threshold value v1, for example, the switch 2 is connected and the ratio is changed.
較的短い時定数を有する時定数回路３を経て検波器１の
出力電圧がＡＧＣ出力となる。このようにして入力電圧
の速い変動に追従した信号制御を行なう。The output voltage of the detector 1 becomes an AGC output via a time constant circuit 3 having a relatively short time constant. In this way, signal control that follows fast fluctuations in input voltage is performed.
この状態のま＼では第２図のように、被制御信号は、発
振を生じ振幅変調を受けた波形となってしまうと思われ
るが、実はそれと同時に被制御入力の振幅はＡＧＣの作
用で減少するので検波器６の出力も低下し値ｖ１以下に
なってしまう。したがＬ
ってスイッチ２は断とな多スイソチ４春接となるので第
３図のようなＡＧＣ特性を与える時定数回路５に切替わ
る。この切替えは短時間に行なわれるので総合的には第
４図のような、ＡＧＣ特門を示すＡＧＣ出力波形となる
０
本発明によれば、以上説明したように、ＡＧＣループが
発振すること々く、立上シ時間を短縮することができる
。In this state, as shown in Figure 2, it is thought that the controlled signal will oscillate and become an amplitude-modulated waveform, but at the same time, the amplitude of the controlled input actually decreases due to the action of AGC. Therefore, the output of the detector 6 also decreases to below the value v1. However, at L, the switch 2 becomes disconnected and connected to four springs, so the circuit switches to the time constant circuit 5 which provides the AGC characteristics as shown in FIG. Since this switching is performed in a short time, the overall result is an AGC output waveform that shows the AGC special mode as shown in FIG. 4. According to the present invention, as explained above, the AGC loop does not oscillate. This makes it possible to shorten start-up time.
なお、上、記実施例では、時定数回路を長、短時定数回
路２個としたが必要に応じてさらにこれを３個以上にす
ることもできる。In the above embodiment, the time constant circuits are two long and short time constant circuits, but the number can be three or more if necessary.
また増幅器７を省いて時定数切換器にその機能を含めた
ものとすることができる。Furthermore, the amplifier 7 can be omitted and its function can be included in the time constant switcher.
第１図は、本発明の実施例を示すブロック図である。
第２図は、同ブロックにおける短い時定数回路のみを使
用し、ＡＧＣループが発振をおこした時の被制御信号波
形を示す。
第３図は、同様に、長い時定数のみを使用した時の被制
御信号波形を示す。
第４図は本発明を実施した時の被制御信号波形を示す。
１．６・・・検波器、２，４・・・スイッチ、３．５・
・・時定数回路、７・・・直流増幅器、８・・・時定数
切替器、９・・・被制御入力、１０・・・ＡＧＣ出力０
特許出願人 日本無線株式会社
才１図
牙 ２１！１
第３笥
牙４１！１FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 shows the controlled signal waveform when the AGC loop oscillates using only the short time constant circuit in the same block. FIG. 3 similarly shows the controlled signal waveform when only a long time constant is used. FIG. 4 shows the controlled signal waveform when the present invention is implemented. 1.6...Detector, 2,4...Switch, 3.5...
... Time constant circuit, 7... DC amplifier, 8... Time constant switch, 9... Controlled input, 10... AGC output 0 Patent applicant: Japan Radio Co., Ltd. Sai1 Zuga 21! 1 3rd Bakuga 41!1
Claims (1)
器１，６とその一方の検波器１の出力側にスイッチ２，
４を介して夫々並列に接続された短および長時定数回路
３．５と、他方の検波器６の出力側に増幅器７を介して
接続された時定数切換器８とから成り、前記時定数回路
３，５の出力側を前記ループのＡＧＣ出力側に接続し、
高い電圧が前記被制御入力側に印加され該ＡＧＣループ
が動作を開始するときに前記時定数切換器８が動作して
前記スイッチ２を接として、前記短時定数回路３を前記
ループに接続し、次にＡＧＣ作用によシ前記被制御入力
側の電圧が低くなると、前記時定数切換器８が動作して
前記スイッチ４を接とするようにしたことを特徴とする
ＡＧＣ回路０Two detectors 1 and 6 are connected to the controlled input side in the AGC loop, and a switch 2 is connected to the output side of one of the detectors 1.
4, and a time constant switch 8 connected to the output side of the other detector 6 via an amplifier 7. Connecting the output sides of circuits 3 and 5 to the AGC output side of the loop,
When a high voltage is applied to the controlled input side and the AGC loop starts operating, the time constant switch 8 operates to connect the switch 2 and connect the short time constant circuit 3 to the loop. Then, when the voltage on the controlled input side becomes low due to AGC action, the time constant switch 8 operates to close the switch 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11968081A JPS5820018A (en) | 1981-07-30 | 1981-07-30 | Agc circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11968081A JPS5820018A (en) | 1981-07-30 | 1981-07-30 | Agc circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5820018A true JPS5820018A (en) | 1983-02-05 |
Family
ID=14767385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11968081A Pending JPS5820018A (en) | 1981-07-30 | 1981-07-30 | Agc circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5820018A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03502278A (en) * | 1989-04-27 | 1991-05-23 | モトローラ・インコーポレーテッド | AGC based on digital signal processor |
| WO1998025340A1 (en) * | 1996-12-06 | 1998-06-11 | Nippon Telegraph And Telephone Corporation | Automatic dynamic range controlling circuit |
-
1981
- 1981-07-30 JP JP11968081A patent/JPS5820018A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03502278A (en) * | 1989-04-27 | 1991-05-23 | モトローラ・インコーポレーテッド | AGC based on digital signal processor |
| WO1998025340A1 (en) * | 1996-12-06 | 1998-06-11 | Nippon Telegraph And Telephone Corporation | Automatic dynamic range controlling circuit |
| EP0944166A1 (en) * | 1996-12-06 | 1999-09-22 | Nippon Telegraph And Telephone Corporation | Automatic dynamic range controlling circuit |
| EP0944166A4 (en) * | 1996-12-06 | 2004-12-29 | Nippon Telegraph & Telephone | Automatic dynamic range controlling circuit |
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