JPS58197855A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58197855A JPS58197855A JP8093982A JP8093982A JPS58197855A JP S58197855 A JPS58197855 A JP S58197855A JP 8093982 A JP8093982 A JP 8093982A JP 8093982 A JP8093982 A JP 8093982A JP S58197855 A JPS58197855 A JP S58197855A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- nitride film
- plasma nitride
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置・製造方法、特にアルミニウムを主
配線金属として用いた多層配線構造の半導体装置におい
て、その）（ツシベーシ璽ン膜としてプラズマ化学成長
（Ｐ ＣＶＤ）法に依シ形成された窒化硅素膜（以下プ
ラズマ窒化膜と称す）を用いた半導体装置の製造方法に
関するものである０プラズマ窒化膜は、化学的成長（Ｃ
ＶＤ）法で形成された酸化硅素膜や、窒化硅素膜に比べ
下地段差における被咎性（以下、ステップカバレッジと
呼ぶ）が良い事、及び被膜の形成が３００℃程度の比較
的低温で可能であり、アルミニウムを主成分とする配線
のヒロックの発生に対して有効である事等の理由により
、大規模集積回路の層間絶縁膜やバッジページ璽ン膜と
して用いられている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices and manufacturing methods, particularly semiconductor devices having a multilayer wiring structure using aluminum as the main wiring metal. This relates to a method for manufacturing a semiconductor device using a silicon nitride film (hereinafter referred to as a plasma nitride film) formed using a silicon nitride film.
Compared to silicon oxide films and silicon nitride films formed by the VD) method, it has better resistance to step coverage at underlying steps (hereinafter referred to as step coverage), and the film can be formed at a relatively low temperature of about 300°C. It is used as an interlayer insulating film and a badge page sealing film for large-scale integrated circuits because it is effective against the occurrence of hillocks in wiring whose main component is aluminum.
ところが、アルミニウム（Ａｌ）を主成分とする配春金
属と該プラズマ窒化膜が直接接触する従来の構造では、
日本国公開特許公報、昭５６−４０２６０号で指適され
ているように、該接触界面の一部において４５０℃乃至
５００”Ｏの熱処理でＡＩ元素がプラズマ窒化膜内へ容
易に拡散に反応し、層間シ璽−トや配線の断線を誘発す
る。However, in the conventional structure in which the plasma nitride film is in direct contact with the spring metal mainly composed of aluminum (Al),
As pointed out in Japanese Patent Publication No. 56-40260, heat treatment at 450°C to 500"O at a part of the contact interface causes the AI element to easily react and diffuse into the plasma nitride film. , leading to breakage of interlayer sheets and wiring.
この様な故障発生メカニズムに対して、前記特許公報に
於いては、Ａｌ配線とプラズマ窒化膜の間に、両者の拡
散反応を抑制する、例えはチタニウムやタングステン、
タンタル等の第２の金属層を形成する事が提案されてい
る。確かに、前記製造方法に依ればＡＩとプラズマ窒化
膜の拡散９反応は抑止する事が出来層間シ冒−トや配線
の断線は防止する事が出来るが、他方新らたな問題が生
ずる。即ち、第２の金属を導入する事に依って、配線パ
ターンを形成すゐためにＡＩのエツチングと同時に第２
金属もエツチング除去しなければならないが、一般に該
第２の金属膜は下地段差部で残夛やすく、延いては配線
間シ嘗−トを引起し歩留りの低下を招く恐れがある。こ
の様な欠点に対して筆者は、＃Ｉ１図に示す如くプラズ
マ窒化膜４とＡＩ配線３との間にプラズマ窒化膜の下敷
としてＣＶＤｒＩｋ化硅帛膜２を敷く方法を試みた。こ
の方法によれば配線上面の平坦部に於けるＡＩ−プラズ
マ窒化膜の拡散１反応は抑える事が出来確かに効果はあ
る。しかし配線側面部は、ＣＶＤ酸化酸化膜素膜２テッ
゛７°カバレッジが悪く一様に配線全体をＣＶＤ酸化酸
化膜素膜２う事が出来ず局所的に１配線とプラズマ窒化
膜が配線側面で接触する箇所６が生じる。この結果ＡＩ
とプラズマ窒化膜の拡散９反応を完全に防止する手段と
けならない事が判明した。In response to such a failure mechanism, the above patent publication discloses that a material such as titanium, tungsten, or
It has been proposed to form a second metal layer such as tantalum. It is true that the above manufacturing method can suppress the diffusion9 reaction between AI and plasma nitride film, and prevent interlayer strikes and wiring breaks, but new problems arise. . That is, by introducing a second metal, the second metal can be etched simultaneously with the AI etching to form a wiring pattern.
Metal must also be removed by etching, but generally the second metal film tends to remain on the underlying step portion, which may eventually cause spots between interconnections and reduce yield. To address these drawbacks, the author tried a method of laying a CVDrIk silicon oxide film 2 between the plasma nitride film 4 and the AI wiring 3 as an underlay of the plasma nitride film, as shown in Figure #I1. According to this method, the diffusion 1 reaction of the AI-plasma nitride film in the flat portion of the upper surface of the wiring can be suppressed, and it is certainly effective. However, the CVD oxide oxide film on the side surface of the wiring has poor 7° coverage, making it impossible to uniformly cover the entire wiring with the CVD oxide film 2. A contact point 6 is generated. This result AI
It has been found that a means to completely prevent the diffusion 9 reaction of the plasma nitride film is essential.
本発明の目的は、これらの欠点を除去、改善するもので
、化学的に安定な酸化アルミニウム膜を陽極酸化法に依
って、配線側面を含む配線表面に一様に形成し、その後
、プラズマ窒化膜を成長する事を特徴とする。The purpose of the present invention is to eliminate and improve these drawbacks.The purpose of the present invention is to uniformly form a chemically stable aluminum oxide film on the wiring surface including the side surfaces of the wiring by an anodic oxidation method, and then to apply plasma nitridation. It is characterized by growing a film.
本発明における酸化アルミニウム膜は、Ａｌ配４１ｔ＝
パターンニング後、陽極酸化によって形成するため、ト
ランジスターや抵抗体が作り込まれている半導体基板と
電気的に導通が保たれていなければならない。従って、
多層配線構造の半導体装置においてその効果が最も良く
発揮される工程は、全配線パターンの接続が完了する最
上層の、ｌ配線層とその後、半導体チップ保線のため、
ポンディングパッド部を除くチップ全域をカバーするパ
ッゾベーシ冒ン膜に対してである。しかし、最上
１層配線よシ下層のＡＩ配線と層間絶縁物として用
いたプラズマ窒化膜に対しても、配線パターンが半導体
基板から電気的導通が保たれるように予め考慮しておけ
ば同様の効果が期待出来る。以下説明の簡素化のため本
発明の実施例を、最上層１配線とパッジページ璽ン膜に
限定に説明する０第２図が本発明の実施例の断面図であ
り、最上層配線ａｔ−ハターンニコンして形成し良後、
その表面全体を陽極酸化で酸化アルミニウム１５で覆う
。The aluminum oxide film in the present invention has an Al arrangement 41t=
Since it is formed by anodic oxidation after patterning, electrical continuity must be maintained with the semiconductor substrate in which transistors and resistors are built. Therefore,
In a semiconductor device with a multilayer wiring structure, the process in which the effect is best exhibited is the uppermost layer (l wiring layer) where all the wiring patterns are connected, and then the semiconductor chip wiring maintenance process.
This is for a pazzobasic film that covers the entire chip area except for the bonding pad area. However, Mogami
A similar effect can be expected for first-layer wiring, lower-layer AI wiring, and plasma nitride film used as an interlayer insulator, if consideration is given in advance to maintain electrical continuity between the wiring pattern and the semiconductor substrate. I can do it. In order to simplify the explanation, the embodiment of the present invention will be described below with reference to the uppermost layer 1 wiring and the pad page sealing film. FIG. 2 is a sectional view of the embodiment of the present invention, and the uppermost layer wiring at After forming a hatern Nikon,
The entire surface is covered with aluminum oxide 15 by anodizing.
シカる彼、パッジベージ冒ンとしてのプラズマ窒化膜４
を成長して、ＡＩとプラズマ窒化膜が直接接触しないよ
うにしたものである。ここで当然最上層配線層以下の各
下層配線層はそれぞれの層間絶縁膜によって分離絶縁さ
れ、且つ電気回路を構成する九めに必要な箇所は、層間
絶縁膜に開孔されたスルーホールを介して電気的接触が
とられている事は云うまでないが図では省略しである。Shikaru He, Plasma Nitride Film 4 as Pudgebage Attack
is grown to prevent direct contact between the AI and the plasma nitride film. Of course, each lower wiring layer below the top wiring layer is isolated and insulated by its own interlayer insulating film, and the ninth necessary parts of the electric circuit are connected through through holes made in the interlayer insulating film. Needless to say, electrical contact is made between them, but this is omitted in the figure.
本発明の方法によれば、第２図に示した如く、配線側面
を含めた配線表面全体を一様な酸化アルミニウム膜で被
接する事が可能であり、その膜厚も陽極酸化の際に外部
から印加する電圧や溶液の種類濃度を適当に選択する事
によって、ＡＩをプラズマ窒化膜の拡散・反応を抑止す
るに充分な膜厚を制御する事は容易である。According to the method of the present invention, as shown in FIG. 2, it is possible to cover the entire wiring surface including the wiring side surface with a uniform aluminum oxide film, and the thickness of the film can be adjusted to the outside during anodization. By appropriately selecting the voltage to be applied and the type and concentration of the solution, it is easy to control the thickness of the AI to be sufficient to suppress the diffusion and reaction of the plasma nitride film.
そのためプラズマ窒化膜をパッジページｌン腋として形
成しても、ＡＪ？配線とプラズマ窒化ｓＦｉ、化学的に
安定な酸化アルミニウム膜によってｉとプラズマ窒化膜
の拡散・反応が阻止される。その結果、従来構造で発生
したｉ配線パターンの局所的な消失やＡＩ配線の断線を
防ぐ事が出き。Therefore, even if a plasma nitride film is formed as a pudge page armpit, the AJ? Diffusion and reaction between i and the plasma nitride film are prevented by the wiring, plasma nitride sFi, and chemically stable aluminum oxide film. As a result, it is possible to prevent the local disappearance of the i-wiring pattern and disconnection of the AI wiring, which occur in conventional structures.
半導体装置の品質を一段と向上する事が可能となる。し
かも、この為に追加しなければならない工程は、特別な
写真食刻工程を含むものでなく、従って新らたな写真食
刻用マスクも必要としない。It becomes possible to further improve the quality of semiconductor devices. Moreover, the steps that must be added for this purpose do not include a special photolithography process, and therefore no new photolithography mask is required.
総合的に見れば従来と同程度の工程数で実現できる０
本発明による他のもう一つの長所は配線間シ冒−トも同
時に防止する事が出来、歩留シの向上が計れる事にある
。即ち、実際の半導体装置の表面は、最上層配線パター
ンを形成するまでの間に経って来た多くの工程によって
複雑で急峻な段差を有しているのが一般的である。一方
微細配線のパターンコングに近年多く用いられている。Overall, this can be achieved with the same number of steps as the conventional method.Another advantage of the present invention is that it can also prevent wire-to-wire strikes, improving yield. . That is, the surface of an actual semiconductor device generally has complicated and steep steps due to the many steps that have taken place before forming the uppermost layer wiring pattern. On the other hand, in recent years, it has been widely used in patterned Kongs for fine wiring.
プラズマ反応型ドライエツチング装置では、これらの段
差部にＡ７Ｉが残りやすい傾向がある。下地段差部を隣
接した最上層配線が通る箇所でＡｌ残りが生じると、互
いに導通状態とな９目的とすゐ回路機能を失ってしまう
。従来、この様なＡＪ残シを完全に除去するためにプラ
ズｆｆＡｊエツチング後、更に溶液を用いたウェットエ
ツチングを追加して隣接配線を分離していた。本発明を
この状態に適用すれば段差部に残ったＡＪは通常わずか
な厚さであるため、容易に酸化アル１＝ウムに変換され
て隣接した配線は互いに絶縁され良状態が可能となる。In plasma reaction type dry etching equipment, A7I tends to remain on these stepped portions. If Al remains at a location where an adjacent top layer wiring passes through the base level difference portion, the wiring will become electrically conductive with each other and the circuit function will be lost. Conventionally, in order to completely remove such AJ residue, after plasma ffAj etching, wet etching using a solution was further added to separate adjacent wirings. If the present invention is applied to this condition, the AJ remaining at the stepped portion is usually of a small thickness, so it is easily converted to aluminum oxide, and adjacent wirings are insulated from each other, making it possible to maintain a good condition.
以上、実施例との説明では最上層配線全綱としてアルミ
ニウムの場合について述べたが、ＡＪとグツズｉ窒化膜
の拡散・反応はＡＪ中に他の金属例えば銅やシリコンを
混入させ＆ＡＡｔを主成分とする配線層や、シリコン、
チタン、タングステン。In the above explanation of the embodiment, we have described the case where aluminum is used as the entire top layer wiring, but the diffusion and reaction between AJ and the Gutsuzu i nitride film involves mixing other metals such as copper and silicon into AJ and making AAt the main component. wiring layer, silicon,
titanium, tungsten.
タンメル婢をＡｌの下敷にした配線との間でも発生し、
本発明の方法はこれらの配線に対して有効な手段となる
。又、配線表面に陽極酸化によって形成する酸化アルミ
ニウムも、無孔性タイプと有孔性タイプの２種類がある
が、どちらのタイプでも有効である。その選択は前述し
た段差部に残るＡｌの程度と陽極酸化で酸化アル＜＝ラ
ムに変換される膜厚郷プロセス全体の系を考慮して決定
すれば良い。It also occurs between wires that are covered with aluminum,
The method of the present invention is an effective means for these wirings. There are also two types of aluminum oxide formed on the wiring surface by anodic oxidation: a non-porous type and a porous type, and either type is effective. The selection may be made in consideration of the amount of Al remaining in the stepped portion and the overall system of the membrane process in which aluminum oxide is converted into aluminum oxide by anodic oxidation.
従って、配線金属をアルミニウムだけに限定したり、酸
化アルミニウムのタイプに制限を加えるものではない。Therefore, the wiring metal is not limited to aluminum only, nor is there any restriction to the type of aluminum oxide.
第１図は従来の方法において、ｌ配線とプラズマ窒化膜
の間にＣＶＤ酸化硅素膜を敷いた場合の断面図。第２図
は本発明の実施例の方法による断面図を示すものである
。
図において、ｌ・・・・・・多層配線構造における最上
層配線とその下に位−する下層配線との層間絶縁物、２
・・・・・・ＣＶＤ酸化膜、３・・・・・・最上層配線
、４・・・・・・プラズマ窒化膜、５・・・・・・陽極
酸化によって配線表面に形成された酸化アルミニウム膜
を示す。
図中同一材質の部分には同一番号を付けである。
、ε１シー ノ し］
茅２２ 目FIG. 1 is a cross-sectional view of a conventional method in which a CVD silicon oxide film is laid between an l wiring and a plasma nitride film. FIG. 2 shows a cross-sectional view of a method according to an embodiment of the present invention. In the figure, l: interlayer insulator between the uppermost layer wiring and the lower layer wiring in a multilayer wiring structure, 2
...CVD oxide film, 3...Top layer wiring, 4...Plasma nitride film, 5...Aluminum oxide formed on the wiring surface by anodic oxidation The membrane is shown. In the figures, parts made of the same material are given the same numbers. , ε1 sea no shi] Kaya 22nd
Claims (1)
ルミニウムである半導体装置において、該最上層配線を
パターンコングする工程と、ノ（ターニングされ九配線
表面を陽極酸化によって酸化アルミニウムに変換する工
１と、プラズマ窒化硅素膜を成長する工程を含む事を特
徴とする半導体装置の製造方法。In a semiconductor device having a multilayer wiring structure in which the top layer wiring metal is aluminum, the top layer wiring is patterned, and the turned wiring surface is converted into aluminum oxide by anodic oxidation. A method for manufacturing a semiconductor device, comprising the step of growing a plasma silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8093982A JPS58197855A (en) | 1982-05-14 | 1982-05-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8093982A JPS58197855A (en) | 1982-05-14 | 1982-05-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58197855A true JPS58197855A (en) | 1983-11-17 |
Family
ID=13732436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8093982A Pending JPS58197855A (en) | 1982-05-14 | 1982-05-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58197855A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63265286A (en) * | 1987-04-23 | 1988-11-01 | セイコーエプソン株式会社 | Active matrix liquid crystal panel |
| US5126283A (en) * | 1990-05-21 | 1992-06-30 | Motorola, Inc. | Process for the selective encapsulation of an electrically conductive structure in a semiconductor device |
| US5164339A (en) * | 1988-09-30 | 1992-11-17 | Siemens-Bendix Automotive Electronics L.P. | Fabrication of oxynitride frontside microstructures |
-
1982
- 1982-05-14 JP JP8093982A patent/JPS58197855A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63265286A (en) * | 1987-04-23 | 1988-11-01 | セイコーエプソン株式会社 | Active matrix liquid crystal panel |
| US5164339A (en) * | 1988-09-30 | 1992-11-17 | Siemens-Bendix Automotive Electronics L.P. | Fabrication of oxynitride frontside microstructures |
| US5126283A (en) * | 1990-05-21 | 1992-06-30 | Motorola, Inc. | Process for the selective encapsulation of an electrically conductive structure in a semiconductor device |
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