JPS58192320A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58192320A
JPS58192320A JP57075165A JP7516582A JPS58192320A JP S58192320 A JPS58192320 A JP S58192320A JP 57075165 A JP57075165 A JP 57075165A JP 7516582 A JP7516582 A JP 7516582A JP S58192320 A JPS58192320 A JP S58192320A
Authority
JP
Japan
Prior art keywords
layer
single crystal
substrate
amorphous
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57075165A
Other languages
Japanese (ja)
Other versions
JPS6341210B2 (en
Inventor
Yasuo Kunii
泰夫 国井
Michiharu Tanabe
田部　道晴
Kenji Kajiyama
梶山　健二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57075165A priority Critical patent/JPS58192320A/en
Publication of JPS58192320A publication Critical patent/JPS58192320A/en
Publication of JPS6341210B2 publication Critical patent/JPS6341210B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Optics & Photonics (AREA)
  • Drying Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To enable the formation of an Si layer with excellent crystallinity by a method wherein the surface of a single crystal Si substrate is treated with HCl up to the temperature of the deposition of amorphous Si after being heat- treated by hydrogen and cleaned. CONSTITUTION:A spontaneous oxide film on the single crystal Si substrate is removed by heating the substrate to 1,100 deg.C or more in the atmosphere of high purity H2. Successively, the substrate is cooled down to 600 deg.C or less. At the temperature over 600 deg.C, it turns poly Si, and therefore amorphous Si of good quality is not depositioned. Thereat, utilizing etching effect by HCl, the surface is prevented from being re-contaminated by impurities in the atmosphere during cooling. An amorphous Si is vapor-grown on a clean Si surface and annealed, and thus the Si layer is formed by solid phase epitaxial growth. By this constitution, the single crystal Si layer of good crystallinity without the disorder of surface shapes can be obtained.

Description

【発明の詳細な説明】 不発明に単結晶子導体基板上わるいはその表向の一部に
絶縁物層を形成した単結晶半導体基板上に気相成長法音
用いて非晶負半導体層全形成しエピタキシャル１１１．
長させることにより単結晶化する半導体装置の製造方法
に関するものでめる。[Detailed Description of the Invention] Uninventively, an amorphous negative semiconductor layer is entirely formed on a single crystalline conductor substrate or on a single crystal semiconductor substrate with an insulating layer formed on a part of its surface using a vapor phase growth method. Form epitaxial layer 111.
This article relates to a method of manufacturing a semiconductor device which is made into a single crystal by increasing the length of the semiconductor device.

従来、気相＆長法會用い１率鮎晶午尋捧基板上に非晶質
半導体層を形成し、エピタキシャルＦｌｉｃ長させるこ
とにより単結晶化した半導体装置の製造方法としては、
尚温処理を用いたいくつかの方法が提案されていた。Conventionally, as a manufacturing method of a semiconductor device in which an amorphous semiconductor layer is formed on a 1-rate Ayu crystal substrate using a vapor phase & long method, and is made into a single crystal by epitaxial film length,
Several methods using still temperature treatment have been proposed.

その１つは、＾温固相成長法である。この従来法は、単
結晶シリコン基板あるいはそり衣（３）の一部に絶縁物
層【形成した単結晶シリコン基板上６５０℃以下の温度
に加熱した後、／クロルシランガスを熱分解して基板上
に非晶質シリコン層を形成し、これを１１００℃以上の
面一に加熱することによっで固相成長でせ単結晶化する
方法である。この従来法においては、非晶質７１７３７
層堆積前に単結晶シリコン基板表面の目然緻化脱を除去
していないため、熱処理の初期以南で非晶質シリコン層
が固相エピタキシャル成長せずに多結晶化してしまい、
　１１００℃以上の両温でも同相成長速度が遅く、また
単結晶化した部分の結晶性も悪くなるという欠点かめっ
た〇また高温加熱のため絶縁物層上の非晶質７リコン層
が多結晶化してしまい、絶縁物層上の非晶質シリコン層
はほとんと同相エピタキシャル成長しないという欠点も
あった０ これらの欠点を除去するために、溶融成長法も用いられ
ていた０これは上記方法と同様に形成した単結晶シリコ
ン基板あるいはその表面の一部に絶縁物層を形成した単
結晶シリコン基板上の非晶質シリコン層にレーサービー
ム又は電子ビームを照射することによシ融点以上の高温
に加熱し、溶融した非晶質シリコンが固化する際ニ液相
エピタキシャル成長させ単結晶化する方法である。この
方法によれは、単結晶基板および絶縁物層上に比較的良
質の単結晶層が得られるか、１１Ｉ！触時に表面形状が
乱れるという欠点があった。One of them is the ^temperature solid phase growth method. This conventional method involves heating a single crystal silicon substrate or a part of the sled (3) to a temperature of 650°C or less to form an insulating layer, and then thermally decomposing /chlorosilane gas onto the substrate. In this method, an amorphous silicon layer is formed on the substrate, and the layer is heated uniformly to a temperature of 1,100° C. or more to achieve solid phase growth and single crystallization. In this conventional method, amorphous 71737
Since the apparent de-densification of the single crystal silicon substrate surface was not removed before layer deposition, the amorphous silicon layer did not undergo solid phase epitaxial growth and became polycrystalline after the initial stage of heat treatment.
The in-phase growth rate is slow even at temperatures above 1,100°C, and the crystallinity of the single-crystalline portion is also poor.Also, due to high-temperature heating, the amorphous 7-Li layer on the insulating layer becomes polycrystalline. There was also the drawback that the amorphous silicon layer on the insulator layer hardly grew in-phase epitaxially.To eliminate these drawbacks, the melt growth method was also used.This is similar to the method described above. The formed single-crystal silicon substrate or the amorphous silicon layer on the single-crystal silicon substrate with an insulating layer formed on a part of its surface is heated to a high temperature above its melting point by irradiating a laser beam or an electron beam. In this method, when molten amorphous silicon solidifies, it undergoes two-liquid phase epitaxial growth to become a single crystal. Depending on this method, a relatively good quality single crystal layer can be obtained on a single crystal substrate and an insulating layer, or 11I! There was a drawback that the surface shape was disturbed when touched.

このように従来法でに、気相成長法によシ形成した非晶
質半導体層から結晶性の艮く炊面形　　　　　１状の乱
れのない単結晶ｍ’ｉ形成した半導体装置１に製造する
ことが困難でめった０ 本発明はこれらの欠点を除去するため、単結晶半導体基
板または一部表面に絶縁物層を形成した単結晶半導体基
板の篇出している表ｔｈを清浄な状１１ＫＬ九後、気相
成長法により非晶質半導体層を形成し、アニールによっ
て同相エピタキシャル成長させることＶｉ−特徴とする
もので。In this way, by the conventional method, a semiconductor device 1 is manufactured from an amorphous semiconductor layer formed by a vapor phase growth method to form a single crystal m'i with a smooth surface shape and no disorder. In order to eliminate these drawbacks, the present invention has been developed by cleaning the exposed surface of a single crystal semiconductor substrate or a single crystal semiconductor substrate with an insulating layer formed on a portion of the surface in a clean state after 11KL. , an amorphous semiconductor layer is formed by a vapor phase growth method, and the in-phase epitaxial growth is performed by annealing.

その目的社結晶性がすぐれ表面形状の乱れのない単結晶
半導体層を単結晶半導体基板または絶縁物層上に形成す
ることにある。The purpose is to form a single crystal semiconductor layer with excellent crystallinity and no disturbance in surface shape on a single crystal semiconductor substrate or an insulator layer.

前記の目的を達成するため、不発＠８は畢結晶半導体基
板Ｖｃｌ！面の自然鐵イ１１除去する水木熱処１ｌｔ−
行い、次に非晶質半導体を堆積する温度まで塩化水素処
理を行うことによシ該基板表面を清浄化することを特徴
とする半導体装置の製造方法を発明の散旨とするもので
ある。In order to achieve the above-mentioned purpose, the misfire@8 is a low-crystalline semiconductor substrate Vcl! Mizuki Heat Treatment 1lt- to remove surface natural iron 11
The gist of the invention is to provide a method for manufacturing a semiconductor device, characterized in that the surface of the substrate is cleaned by performing a hydrogen chloride treatment to a temperature at which an amorphous semiconductor is deposited.

次に本発明の実施例を象附図面についてＷ！ｉｔ明する
。なお実施例は一つの例示であって、本発明の精神を逸
脱しない範囲内で、楯々の変更あるいは改良ケ行いうる
ことは云うまでもない〇第１図は不発明の実施例を示す
。凶においてｌは単結晶シリコン基板、２は絶縁物層、
３＆は非晶質シリコン層％　３ｂ、３ｃは単結晶シリコ
ン層である。まず単結晶半導体基板として第１図Ａに示
すような単結晶シリコン基板Ｉｔ用いる。次に第１図Ｂ
に示すような絶縁物層（例えば酸化シリコン、ｉＥ化シ
リコン）２を単結晶シリコン基板１の−ｍ表面に形成す
る。次に非−負半導体として非晶質シリコン３ａｔ−清
浄な基板表面上に堆積する。ます前記基板を非晶質シリ
コン堆積用反応炉に入れ、高純度の水素雰囲気中で基板
１１１００℃以上に加熱し、シリコン表面の自然酸化ｌ
［′を除去する。Next, W! It will be clear. It should be noted that the embodiments are merely illustrative, and it goes without saying that the shields may be modified or improved without departing from the spirit of the invention. FIG. 1 shows an embodiment of the present invention. 1 is a single crystal silicon substrate, 2 is an insulating layer,
3& is an amorphous silicon layer% 3b and 3c are single crystal silicon layers. First, a single crystal silicon substrate It as shown in FIG. 1A is used as a single crystal semiconductor substrate. Next, Figure 1B
An insulator layer (for example, silicon oxide, iE silicon) 2 as shown in FIG. 1 is formed on the -m surface of a single crystal silicon substrate 1. Amorphous silicon 3at- is then deposited on the clean substrate surface as a non-negative semiconductor. First, the substrate is placed in a reactor for amorphous silicon deposition and heated to 1100°C or higher in a high-purity hydrogen atmosphere to remove natural oxidation on the silicon surface.
[Remove ′.

シリコン表面の自然改化換を除去した後、良質な非晶質
シリコンが堆積可能な６００℃以千の温度までシリコン
基板を冷却する（６００℃以上では多結晶半導体となっ
てしまうン。その際にシリコン表面が雰囲気中の不純物
によって再び汚染されないため１本発明では＃！２図の
ような塩化水素によるシリコンのエツチング効果を用い
る。After removing natural modification on the silicon surface, the silicon substrate is cooled to a temperature above 600°C at which high-quality amorphous silicon can be deposited (at temperatures above 600°C, it becomes a polycrystalline semiconductor. In order to prevent the silicon surface from being contaminated again by impurities in the atmosphere, the present invention uses the etching effect of silicon by hydrogen chloride as shown in Figure #!2.

第２図は、横軸に試料温度をとり、縦軸に各種ガスによ
るエツチング速度をプロットしたものである。４はアル
ゴン希釈塩化水素０．５％。FIG. 2 plots the sample temperature on the horizontal axis and the etching rate by various gases on the vertical axis. 4 is 0.5% hydrogen chloride diluted with argon.

５はアルゴン希釈塩化水素０．ＩＮ、６は水素ガスによ
るシリコンのエツチング速度に＆す。以上のエツチング
速度は、当該の温度におけるエツチングに先立って水素
雰囲気中で１１００℃以上に加熱し、自然酸化換金除去
した上で求めｆｃ甑である。これに対して７は自然酸化
膜ケ除去しない場合のアルゴン希釈塩化水素０．１Ｘに
よるエツチング速度であり、その甑は自然酸化膜倉除去
した場合に比べ著しく減少している。第２図かられかる
ように水素雰囲気で１１００’Ｃ以上に加熱した後、塩
化水素上台む雰囲気中たとえはアルゴン希釈塩化水素０
．１Ｘ！Ｉ囲気中で冷却すれば６００℃以下の＠度でも
清浄なシリコン六向會形敗できる。5 is argon diluted hydrogen chloride 0. IN, 6 is the etching speed of silicon by hydrogen gas. The above etching rate is determined by heating to 1100° C. or higher in a hydrogen atmosphere to remove natural oxidation and conversion prior to etching at the relevant temperature. On the other hand, 7 is the etching rate using argon-diluted hydrogen chloride 0.1X when the natural oxide film is not removed, and the etching rate is significantly reduced compared to when the natural oxide film is removed. As shown in Figure 2, after heating to 1100'C or higher in a hydrogen atmosphere, in an atmosphere over hydrogen chloride, for example, argon diluted hydrogen chloride 0.
．． 1X! If cooled in an ambient atmosphere, clean silicon can be formed at temperatures below 600°C.

その後第１図Ｃのように６００℃以１の温度たとえは５
５０℃で非晶質シリコンＭ３を気相Ｆｆｃ長させる。気
相成長はたとえはアルゴン希釈シラｙＯ熱分解によシ非
晶質シリコンを成長させる。After that, as shown in Figure 1C, the temperature above 600℃1 is 5
Amorphous silicon M3 is heated to a vapor phase Ffc length at 50°C. In the vapor phase growth, amorphous silicon is grown, for example, by pyrolysis of silica diluted with argon.

６００℃以下で気相成長を行なうことにより、膜中に微
結晶を含まない良質な非晶質シリコン膜上シリコン基板
上に及び絶縁物層上に形成できる。これにより同相エピ
タキシャル成長後の結晶性上良好なものにすることがで
きる。その後適当な＠度例えば６００Ｃで非晶質シリコ
ン層３ａ【アニールし固相エピタキシャル成長させ第１
図りに示すように単結晶シリコン層３ｂにする。By performing vapor phase growth at 600° C. or lower, it is possible to form a high-quality amorphous silicon film containing no microcrystals in the film, on a silicon substrate, and on an insulating layer. This makes it possible to obtain good crystallinity after in-phase epitaxial growth. Thereafter, the amorphous silicon layer 3a is annealed at an appropriate temperature, for example, 600C, and solid phase epitaxial growth is performed.
A single crystal silicon layer 3b is formed as shown in the figure.

アニールを低温で行なえは、基板１と単結晶シリコン層
３ｂの間に不純物１１度分布を形成する場合急峻な分布
を形成することができる。不純物濃度分布はあらかじめ
基板に不純物を含ませたり、気相成長時に非晶質シリコ
ンに不純物を含ませることによ多形成できる。If annealing is performed at a low temperature, a steep impurity distribution can be formed when an 11 degree distribution of impurities is formed between the substrate 1 and the single crystal silicon layer 3b. The impurity concentration distribution can be formed by impurities being added to the substrate in advance or by adding impurities to amorphous silicon during vapor phase growth.

第３図り本発明の他の実施例會示すもので、第１実施例
における絶縁物層を形成せずに行う場合金示すもので、
第３図Ａ、Ｂ、Ｃの工程は　　　　艷。The third diagram shows another embodiment of the present invention, and shows a case where the process is performed without forming an insulating layer in the first embodiment.
The processes in Figure 3 A, B, and C are 艷.

第１図Ｂ、Ｃ，Ｄの各工程と同じように行われるもので
ある。This step is carried out in the same manner as the steps B, C, and D in FIG.

本発明については、単結晶シリコン基板および絶縁物層
上の単結１シリコン層の反射電子線回折像によって結晶
性′ｔ−調べたところこの１ｇＩ折像は菊池パターンと
呼はれる回折ｇＩ′１に含んでおシ結晶性が良好である
ことが認められた０なお、本発明において形成した清浄
なシリコン基板表面上の非晶質シリコン層の場合アニー
ル時にレーザービーム、電子ビーム、筒エネルギー粒子
ビーム及び赤外線アニールｖ！ヲ用いた融点以下の高温
加熱を行なっても非晶質シリコン層が多結晶化する以前
に同相エピタキシャル成長するためこれらのアニール法
も適用Ｃ１１能であり、アニール時間ｔ−煉縮すること
ができる。Regarding the present invention, the crystallinity 't- was investigated by reflection electron diffraction images of a single silicon layer on a single crystal silicon substrate and an insulator layer. In addition, in the case of the amorphous silicon layer formed in the present invention on the surface of a clean silicon substrate, laser beam, electron beam, or cylindrical energetic particle beam was used during annealing. and infrared annealing v! Even if the amorphous silicon layer is heated at a high temperature below its melting point, the in-phase epitaxial growth occurs before the amorphous silicon layer becomes polycrystalline, so these annealing methods can also be applied, and the annealing time can be reduced by t.

その後単結晶半導体層３ｂの一部を除去又は絶縁物化す
ることによシ第１図Ｅに示したように単結晶シリコン層
３ｃｔ基板１と完全に絶縁分離することができる０ 以上説明したように、不発ｑｔ用いれは率結晶半導体層
會単結晶半導体基板上に低温で、あるいはビーム・アニ
ールによれば非常に頬時間で形成できるので、不純物の
拡散による分布のダレのない急峻な不純物濃度分布を単
結晶半導体基板と単結晶半導体層の間に形成することが
できる利点がおる。また本発明を用いれば絶縁物層上に
固相エビクキシャル成長により単結晶半導体層を形成で
きるので、 （イ）単結晶半導体層を単結晶半導体基板と完全に絶縁
分離できる。Thereafter, by removing a part of the single crystal semiconductor layer 3b or converting it into an insulator, the single crystal silicon layer 3b can be completely insulated and separated from the substrate 1 as shown in FIG. 1E. , unexploded qt can be used to form a monocrystalline semiconductor layer on a single crystal semiconductor substrate at a low temperature or by beam annealing in a very short time, so it is possible to create a steep impurity concentration distribution without any sag in the distribution due to impurity diffusion. It has the advantage that it can be formed between a single crystal semiconductor substrate and a single crystal semiconductor layer. Furthermore, by using the present invention, a single crystal semiconductor layer can be formed on an insulating layer by solid-phase evixaxial growth, so (a) the single crystal semiconductor layer can be completely insulated and separated from the single crystal semiconductor substrate.

（ロ）結晶性がすぐれかつ表面形状の乱れのない単結晶
半導体層が形成できる０ 等の利点がある０(b) It has advantages such as the ability to form a single crystal semiconductor layer with excellent crystallinity and no disturbance in surface shape.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図Ａ−ＥＦｉ本発明による半導体装置の製造方法の
概略、第２図はも柚ガスによるシリコンのエツチング速
度、第３図Ａ−Ｃは不発明の他の実施例會示す０ １・・・・・・単結晶シリコン基板、２・・・・・・絶
縁物層、３ａ・・・・・・非晶質シリコン層、３　ｂ　
！　３　ｃ・・・・・・単結晶シリコン層 １図Fig. 1 A-EFi shows an outline of the method for manufacturing a semiconductor device according to the present invention, Fig. 2 shows the etching rate of silicon by citrus gas, and Fig. 3 A-C shows other embodiments of the invention. ...Single crystal silicon substrate, 2...Insulator layer, 3a...Amorphous silicon layer, 3b
! 3 c... Single crystal silicon layer 1 diagram

Claims (3)

【特許請求の範囲】[Claims] （１）　単結晶半導体基板にｔｉｃ向の自然鹸化賑を除
去する水素熱処理を行い、次に＃晶賀千尋捧を堆積する
温度まで塩化水素処理を行うことｙｃよシ該基板課ｉｉ
］會清浄化−ｆゐことｒ特徴とする半導体装置の製造方
法。(1) Hydrogen heat treatment is performed on the single crystal semiconductor substrate to remove natural saponification in the tic direction, and then hydrogen chloride treatment is performed to the temperature at which #ShogaChihirode is deposited.
] A method for manufacturing a semiconductor device characterized by cleaning-f. （２）単結晶半導体基板＆面の水木熱処址の恢、非晶買
手導体會堆積する温度まで清浄な状態ＶＣする第１の清
浄化工機と、該半導体基板上に気相成長法によシロ００
℃以）の温度で非晶質半導体層を形成する第２の堆積工
程と、駁非晶買半導体層をアニールして固相エピタキシ
ャル数量させ単結晶化する第３の熱処理工程とを含むこ
とを特徴とする特ｒｔａ＊求の範囲第１項記載の半導体
装置の製造方法。(2) Based on the Mizuki heat treatment site of the single crystal semiconductor substrate & surface, the first cleaning equipment performs VC in a clean state up to the temperature at which the amorphous conductor is deposited, and the vapor phase growth method is applied on the semiconductor substrate. Shiro 00
a second deposition step of forming an amorphous semiconductor layer at a temperature of (°C or higher); and a third heat treatment step of annealing the amorphous semiconductor layer to form a solid phase epitaxial layer and converting it into a single crystal. Features: A method for manufacturing a semiconductor device according to item 1. （３）単結晶半導体基板衆囲の一部に絶縁′＠層を形成
する＠１の工程と、該千都俸基板にふ−いて結晶内の島
田した表面’ｔ”　１１００℃以上のＬ処理後６００℃
以１の温度まで渭浄な状態に保つ第２の清浄工程と、該
半導体基板ｊｌＬ＃ｈＩ＆＆衆面および絶縁物階上に気
相成長法により６００℃以）の温度で非晶質半導体層を
形成する第３の堆積上根と、前配非晶質半導体層會アニ
ールして固相エピタキシャル成長させ単結晶化する第４
の熱処理工程とを含むことを特徴とする特許請求の範囲
第１項ｌＳｅ載の半導体装置の製造方法０（４）前記の
第１乃至第４の工＠後、ｍ５の工程として単結晶化され
た半導体層の−Ｓを絶縁物化することにより完全絶縁分
陰形半導体基板とすることｔ特徴とする待ｉＦｔ請氷の
範囲第３項Ｈｅ載の半導体装置の製造方法。(3) Step 1 of forming an insulating layer on a part of the single-crystal semiconductor substrate, and applying L treatment at 1100°C or higher on the surface of the crystal inside the substrate. After 600℃
A second cleaning step is performed to maintain the semiconductor substrate in a clean state up to a temperature of The third deposited upper layer is formed, and the fourth layer is annealed to form a single crystal by solid phase epitaxial growth.
Claim 1: Method for manufacturing an lSe-based semiconductor device 0 (4) After the first to fourth steps, monocrystallization is performed as step m5. 3. A method for manufacturing a semiconductor device according to claim 3, characterized in that -S of the semiconductor layer is made into an insulator to obtain a completely insulating cathode type semiconductor substrate.
JP57075165A 1982-05-07 1982-05-07 Manufacture of semiconductor device Granted JPS58192320A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57075165A JPS58192320A (en) 1982-05-07 1982-05-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57075165A JPS58192320A (en) 1982-05-07 1982-05-07 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS58192320A true JPS58192320A (en) 1983-11-09
JPS6341210B2 JPS6341210B2 (en) 1988-08-16

Family

ID=13568311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57075165A Granted JPS58192320A (en) 1982-05-07 1982-05-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58192320A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01300521A (en) * 1988-05-30 1989-12-05 Fujitsu Ltd Method and apparatus for manufacturing semiconductor
JP2007516586A (en) * 2003-12-03 2007-06-21 エス．オー．アイ．テック、シリコン、オン、インシュレター、テクノロジーズ Method for improving the surface roughness of a wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01300521A (en) * 1988-05-30 1989-12-05 Fujitsu Ltd Method and apparatus for manufacturing semiconductor
JP2007516586A (en) * 2003-12-03 2007-06-21 エス．オー．アイ．テック、シリコン、オン、インシュレター、テクノロジーズ Method for improving the surface roughness of a wafer

Also Published As

Publication number Publication date
JPS6341210B2 (en) 1988-08-16

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