JPS58191426A - Semiconductor substrate - Google Patents
Semiconductor substrateInfo
- Publication number
- JPS58191426A JPS58191426A JP7488882A JP7488882A JPS58191426A JP S58191426 A JPS58191426 A JP S58191426A JP 7488882 A JP7488882 A JP 7488882A JP 7488882 A JP7488882 A JP 7488882A JP S58191426 A JPS58191426 A JP S58191426A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- epitaxial growth
- slip
- epitaxial
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 title abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052799 carbon Inorganic materials 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 13
- 235000012431 wafers Nutrition 0.000 description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 229910052787 antimony Inorganic materials 0.000 description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 241000238557 Decapoda Species 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000010923 batch production Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 229940003304 dilt Drugs 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はエピタキシャル成長に用いる半導体基板に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor substrate used for epitaxial growth.
半導体基板上に形成したシリコンエピタキシャル−は主
にバイポーラデバイスに用いられる。デバイスとしては
、所望の一岸、不純物一度であることはもらろんのこと
、その膜の均一性や結晶欠陥のない一品質のエピタキシ
ャル験が望まれる。Silicon epitaxial layers formed on semiconductor substrates are mainly used for bipolar devices. As a device, it is desired that the epitaxial process not only be free of impurities, but also have uniform film quality and a high quality epitaxial structure free from crystal defects.
又シリコンエピタキシャルの成長方法には常圧法や減圧
法があシ、加熱方式としては尚周波加熱法中赤外線加熱
法等がある。さらにエピタキシャル城の結晶欠陥として
は積層欠陥、転位、微小欠陥エピタキシャルスリップ、
エピタキシャルマウンド等があシ、楡々の低減方法が提
案されて込る。Further, silicon epitaxial growth methods include a normal pressure method and a reduced pressure method, and heating methods include a high frequency heating method, a mid-infrared heating method, and the like. Furthermore, crystal defects in epitaxial castles include stacking faults, dislocations, micro defects epitaxial slip,
A number of methods have been proposed to reduce the occurrence of burrs and burrs in epitaxial mounds.
本発明はＩＩ！ｌｌ絢波加熱法ｔｉｃおいて大口径ウェ
ハ（４″〜５１φ）１１ｔ用いた場合にデバイスの歩留
シ向上を制限する一曽因であるエピタキシャル成長時の
スリップ発生の抑１方法に関するものである。The present invention is II! This invention relates to a method for suppressing the occurrence of slip during epitaxial growth, which is one of the major causes of limiting improvement in device yield when large-diameter wafers (4'' to 51φ) 11t are used in the 11-wave heating method.
１ＩｈＪｌｉｉＩ波加熱方式扛カーボンサセプタを加熱
し、その上のウェハを間接的に加熱するためにウニへ内
の！！直分布か不均一となシ、反り易くなりスリップが
主にウェハの周辺部から発生する。このスリラフ付近に
はエピタキシャル後のデバイス形成Φ友めの熱処理によ
り転位が鋳起され、デバイスの歩留多低下をもたらす等
の不利な点がある。1IhJliiI wave heating method to heat the carbon susceptor and indirectly heat the wafer above it! ! If the wafer has a direct distribution or is not uniform, it will warp easily and slip will occur mainly from the periphery of the wafer. Dislocations are generated in the vicinity of this srill rough due to heat treatment during device formation after epitaxial formation, which has disadvantages such as a decrease in device yield.
しかるに、囲えば４−＃φウェハの面方位の異な＋−＋
る（１００）、（１１１）、（５１１）のそれぞれＰ
、Ｐ 、ＮＮ＆板を遇び、岡バッチ処理のエピタキ
シャル成員を行い、エピタキシャルスリップの発生率ヲ
―ぺたところ、Ｐｍ＆を用いた場合にのみＯ〜２ｘ以内
０発生率で、他ノウエノｓ（Ｐ 、Ｎ 、Ｎ ）
の揚台にはその発生率ｉ１０〜２０％であった。However, if we enclose 4−
, P, NN& plates, Oka batch process epitaxial members were used, and the occurrence rate of epitaxial slip was found to be 0 within O~2x only when Pm& was used, and other Nouenos (P, N, N)
The incidence rate was 10-20% on the lifting platform.
又エピタキシャル成長前後のウェハの反シの変化を測定
したとζろＰ 基板（板厚〜５００ｊＪｎ）を用いたＮ
エビ（〜１０ｘｍ）の反夛は＋５〜＋ｌ Ｏａｍ＋
上に凸状になっていることが分９、一方ＮＡ板（板ＩＩ
〜５００Ｊｍ）ｔ−用いたＮｚピ（〜１０＊ｍ）の反９
は逆に一４°〜−８μｍ下に凸状になっていることが分
った。この場合Ｐ 基板のときにはｂ１原子よ１も原子
半ＩＩＯ小さめボロンがドーピングされており、エピタ
キシャル成長後凸状になりウェハ内の温度の不均一を緩
和する方向に反）スリン＋
プの発生を抑制できるものであろう。−万Ｎ 基板のと
きには、８点原子よりも原子半径の大きいアンチモンが
ドーパンＦであシ、エピタキシャル成兼後反多が負に変
化し、ウェハ内の温健の不均一を増長する方向であり、
スリップが発生し易くなるものと考えられる。ちなみに
８ム原子の半径は１．３２１．ボロ□ンのそれは８．９
ｄ、アンチモンＯそれ紘１．５９１である。We also measured the change in the wafer's surface resistance before and after epitaxial growth.
The repulsion of shrimp (~10xm) is +5~+l Oam+.
~500Jm) t-Nz pi (~10*m) anti-9
On the contrary, it was found that the shape was convex downward by -4° to -8 μm. In this case, the P substrate is doped with boron, which is one and a half atoms smaller than the b1 atom, and becomes convex after epitaxial growth, which can alleviate the temperature non-uniformity within the wafer and suppress the generation of slin+. It must be something. - 10,000 N In the case of a substrate, antimony with a larger atomic radius than the 8-point atom is doped with F, and after epitaxial formation, the antimony changes negatively, which tends to increase the thermal non-uniformity within the wafer.
It is thought that slips are more likely to occur. By the way, the radius of an 8m atom is 1.321. Boro□n's is 8.9
d, antimony O sorehiro 1.591.
本発明は上記の実験事実に基づいτなされえものである
。The present invention has been made based on the above experimental facts.
＋
Ｐ 基板を用いればスリップ発生の少ないクエ／１を慢
ることが上記の実験夢夾よ）＋ｌＪ明したが、しかるに
バイポーラデバイス用基鈑としてＦｉＰ 基板が用い
られている。上記の事実からもＰ 基板を用いたエピタ
キシャル成長した場合ＫＦｉスリップの発生が多いこと
も分った。It was revealed in the above experiment that using a +P substrate results in Q/1 with less slippage, but FiP substrates are used as substrates for bipolar devices. From the above facts, it was also found that KFi slip occurs frequently when epitaxial growth is performed using a P substrate.
本発明では半導体基板の表面に半導体基板を構成する原
子よりその原子半径が小さく、かつ電気的に不活性な元
素を導入した半導体基板を用いエピタキシャル成長時の
スリップ発生【抑−しデバイスの歩留多向上を目的とす
るものである。In the present invention, a semiconductor substrate having an atomic radius smaller than the atoms constituting the semiconductor substrate and an electrically inert element introduced into the surface of the semiconductor substrate is used to suppress the occurrence of slip during epitaxial growth. The purpose is to improve.
原子半径の小さい元素で且つ電気的に不活性表元素を半
導体基板の裏面に導入した場合、半導体基板は通常裏ｒ
Ｔｉ糊が圧縮応力を受はエビタキシャこれはサセプタと
半導体基板との接触状態が良く＆Ｌ半導体基板の温度の
不均一を緩和する。又電気的に活性なる元素を選べば、
エピタキシャル成長時に半導体基板の裏面から表ＩＩＫ
不純物の再分布（オートドーピングという現象）が起Ｌ
エピタキシャル層の電気的特性が変化するため好ましく
ないが、不活性元素ではこのようなことは起きない。When an element with a small atomic radius and an electrically inert surface element is introduced into the back surface of a semiconductor substrate, the semiconductor substrate is usually
The Ti glue receives the compressive stress due to the evitaxia, which provides good contact between the susceptor and the semiconductor substrate and alleviates non-uniformity in temperature of the semiconductor substrate. Also, if you choose an electrically active element,
From the back side of the semiconductor substrate to the front side IIK during epitaxial growth
Redistribution of impurities (a phenomenon called autodoping) occurs.
This is undesirable because it changes the electrical properties of the epitaxial layer, but this does not occur with inert elements.
以下に本発明の実施ｆ／４について述べる。Implementation f/4 of the present invention will be described below.
４インチの（１１１）方位のＰ 基板を選び、悪処通基
板、基板のｍ面にボロンをその不純物１１１Ｋが〜１０
／−熱拡散したもの、炭翼又は窒素をイオン注入（
２００ｋｖ、 〜０．５ｍｒｎｌさ、ドーｘｌｉ：ｌＸ
１Ｇ／−）Ｌ、そのピークａｍを〜１０７ｃｄとしたも
のを用意する０以上の半導体基板をベルジャｍｌ（高周
波加熱方式）エピタキシャル膜にセットシ、残流量を７
５Ｊ／分として、その基板温度を〜１１５０ｃＫ保ちＨ
Ｃ１ガスエッチ／グを〜３分行う、つづいて基板層ｆを
〜１０５０℃に下げ８ムＨ４（１００Ｎ）を〜５００ｃ
ｃ／分？、−１５分ノ成長テ〜ｌＯ声ｍのエピタキシャ
ル膜が成長する。上記の成長後の半導体基板をジルトル
エツチングを〜５分行ｉ、ウェハ内のエビスリップを干
渉頗黴鏡で一定する。その結果、５ｍｍｘ５ｍｍのチッ
プを想定し、スリップが横切るチップは不良とし、その
ウェハ内でのスリップの面積占有率を採ると、無＃＆境
基板でｔｉ〜２ＯＮの発生が見られ、他の基板層１１＃
ｌｃボロン、炭素、窒素を導入したものは０−２Ｘ以内
であった。しかしボロンの場合にはエピタキシャル成長
時Ｋｌｋ面からのボロンが表面（エピタキシャルＭ）Ｋ
再分布（オートドーピングトモｉう）が起プ、問題とな
夛、裏面のシール等の方法を採る必要かあり繁雑で一般
的でな込、しかし炭素、ｉ！素等は電気的に不活性でエ
ピタキシャル成長中に何ら不都合を生じないことが実験
により分りえ。A 4-inch (111) oriented P substrate is selected, and the impurity 111K is ~10 by adding boron to the m-plane of the substrate.
/-Ion implantation of thermally diffused material, carbon blades or nitrogen (
200kv, ~0.5mrnl, doxli:lx
1G/-)L with a peak am of ~107 cd. Set a semiconductor substrate of 0 or more on a Bellja ml (high frequency heating method) epitaxial film, and set the residual amount to 7.
5J/min and maintain the substrate temperature at ~1150cK.
Perform C1 gas etching for ~3 minutes, then lower the substrate layer f to ~1050°C and apply 8mm H4 (100N) to ~500°C.
c/min? , -15 minutes, an epitaxial film of about 10 m is grown. After the above-described growth, the semiconductor substrate is subjected to dilt etching for ~5 minutes, and the shrimp slip within the wafer is fixed using an interference mirror. As a result, assuming a 5mm x 5mm chip, a chip with a slip across it is considered defective, and when calculating the area occupation rate of the slip within the wafer, the occurrence of ti~2ON was observed on the non-#& border board, and on other boards. Layer 11#
Those into which lc boron, carbon, and nitrogen were introduced were within 0-2X. However, in the case of boron, boron from the Klk plane during epitaxial growth is transferred to the surface (epitaxial M) K
Redistribution (autodoping) occurs, which is a problem, and methods such as sealing on the back are necessary, which is complicated and common, but carbon, i! Experiments have shown that the element is electrically inactive and does not cause any problems during epitaxial growth.
閣は基板裏面に炭素及び窒素を打ち込んだドース量とエ
ビタ中シャル成長ＷｋＫ見られるスリ、プ発生率をプロ
ットしたものであシ、高濃度にイオン注入したものほど
スリップ発生率が小さいことが分った。不純物をイオン
注入しそのドース量がｌＸｌ０ ／ａｉ（ピークｍ度
〜１０ ／ｃｄ）のと自エピタキシャルスリップはほ
ぼ〜ｏｘであった。The figure is a plot of the dose of carbon and nitrogen implanted into the backside of the substrate and the rate of occurrence of slips and slips observed during the growth of Evita. It was. When impurity ions were implanted at a dose of 1X10 /ai (peak m degrees ~10 /cd), the self-epitaxial slip was approximately ~ox.
本夷總鉤ではその基板方位が（１１１） ｊｉＫついて
説明したが、他のｍＴｊ、ｔｉｔｓえば（Ｚｏｏ）、（
５１１） ［ついても同効果が得られることは紀すまて
もない。In the case of Honyi Sohaku, we have explained that the substrate orientation is (111) jiK, but for other mTj, tits, (Zoo), (
511) [It is a shame that the same effect can be obtained even if it is attached.
以上Ｏように大口径ウェハを用いてエピタキシャル成長
を行なう場合に、温１分布の不均一による応力で発生す
るスリップを基板裏面に８に原子よりもその原子半径が
小さく、シかも電気的不活性な炭素、窒素等を高１）［
［導入すること虻よ〕抑制できるもので、バイポーラデ
バイスの高歩留〕を達成できる。When epitaxial growth is performed using a large-diameter wafer as described above, slips caused by stress due to non-uniform temperature distribution may occur on the back surface of the substrate because the atomic radius is smaller than that of the atoms and there may be electrically inactive wafers. High carbon, nitrogen, etc. 1) [
By suppressing the introduction of flies, a high yield of bipolar devices can be achieved.
図は基板層ａｉにイオン注入した不純物のドース量ト、
エピタキシャル成長後のウェハのスリップ弛生率の関係
を示したもので、横軸は不純物のドース量、縦軸紘スリ
ップ発生率である。ムは不純物が炭素、８社窒素の場合
である。
本身（物のドースｔ Ｃｃｍ−２）The figure shows the dose of impurities ion-implanted into the substrate layer ai.
This figure shows the relationship between the slip relaxation rate of a wafer after epitaxial growth, where the horizontal axis is the impurity dose and the vertical axis is the slip occurrence rate. Figure 8 shows the case where the impurities are carbon and nitrogen. Main body (mono dosu t Ccm-2)
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7488882A JPS58191426A (en) | 1982-05-04 | 1982-05-04 | Semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7488882A JPS58191426A (en) | 1982-05-04 | 1982-05-04 | Semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58191426A true JPS58191426A (en) | 1983-11-08 |
Family
ID=13560354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7488882A Pending JPS58191426A (en) | 1982-05-04 | 1982-05-04 | Semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58191426A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5617730A (en) * | 1995-01-30 | 1997-04-08 | Nippondenso Co., Ltd. | Compressor control device for car air conditioner |
-
1982
- 1982-05-04 JP JP7488882A patent/JPS58191426A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5617730A (en) * | 1995-01-30 | 1997-04-08 | Nippondenso Co., Ltd. | Compressor control device for car air conditioner |
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