JPS5818929A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5818929A JPS5818929A JP11694881A JP11694881A JPS5818929A JP S5818929 A JPS5818929 A JP S5818929A JP 11694881 A JP11694881 A JP 11694881A JP 11694881 A JP11694881 A JP 11694881A JP S5818929 A JPS5818929 A JP S5818929A
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- hours
- temperature
- crystal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 36
- 239000013078 crystal Substances 0.000 claims abstract description 19
- 239000011261 inert gas Substances 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 12
- 229910052760 oxygen Inorganic materials 0.000 description 12
- 239000001301 oxygen Substances 0.000 description 12
- 239000007789 gas Substances 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- UREBDLICKHMUKA-CXSFZGCWSA-N dexamethasone Chemical compound C1CC2=CC(=O)C=C[C@]2(C)[C@]2(F)[C@@H]1[C@@H]1C[C@@H](C)[C@@](C(=O)CO)(O)[C@@]1(C)C[C@@H]2O UREBDLICKHMUKA-CXSFZGCWSA-N 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000009528 severe injury Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法のうち、特に無欠陥層（
ｄｅｎｕｄｅｄ ｚｏｎｅ ｒデヌーデッドゾーン）を
形成する熱処履方法番こ関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, in particular a defect-free layer (
This relates to a heat treatment method for forming a denuded zone.
半導体装置の高密度化、鳥集積化に伴って、それを製造
する時に、シリコン（Ｓｉ）基板内に発生する結晶欠陥
が半導体装置の電気的特性を悪くし、製造歩留を低下さ
せる傾向が一層明瞭になって欺た。この結晶欠陥（例え
ば積層欠陥や転位など）を鱈発する原因は、酸素（０１
） 、炭素（Ｑ、重金属などの不純物含有にあることは
良く知られて勘り、特に酸素、炭素はその影響が大糠い
と言われている。As semiconductor devices become denser and more integrated, crystal defects that occur in silicon (Si) substrates tend to deteriorate the electrical characteristics of semiconductor devices and reduce manufacturing yields. It became clearer and more deceiving. Oxygen (01
), carbon (Q, heavy metals, and other impurities) is well known and understood, and it is said that oxygen and carbon are particularly affected by these impurities.
現在、チ冒りラルス中−法（Ｃｚｏｃｈｒａｌｓｋｉ法
；引上法）で作成されるＳ１単結晶には１．ｏ ｘ １
ａｄ程度の酸素量と５ Ｘ １０Ｖ４程度の炭素量の含
有は避けられないことであり、これらは結晶中で過飽和
とな忰析出状態にある。その析出した状態にある例えば
酸素を含んだＳ１単結晶を６００〜８００℃の比較的低
温度で感層すると、凝集して酸化シリコン（８１０゜、
ＸＺ）が析出し、核が形成される。核を含んだｓｉ単結
晶を用いて、半導体装置を製造するための高温度熱処理
を行えば、格子の歪が生じ、転位・積層欠陥を発生して
、半導体装置の特性が低下する。Currently, the S1 single crystal produced by the Czochralski method (Czochralski method; pulling method) has 1. ox 1
It is unavoidable to contain an amount of oxygen on the order of ad and an amount of carbon on the order of 5×10V4, and these are in a supersaturated state of precipitation in the crystal. For example, when the precipitated S1 single crystal containing oxygen is exposed to a layer at a relatively low temperature of 600 to 800°C, it aggregates and forms silicon oxide (810°,
XZ) is precipitated and a nucleus is formed. When a Si single crystal containing nuclei is subjected to high-temperature heat treatment for manufacturing a semiconductor device, lattice distortion occurs, dislocations and stacking faults occur, and the characteristics of the semiconductor device deteriorate.
従って、かような結晶欠陥を除去する方法が種々提案さ
れてｊね、例えば窒素（Ｎ、）ガス雲間気中で６００〜
８００℃の比較的低温で数時間熱処理し、−旦常温に戻
した後、次（こ１０００℃以上の高温で数時間熱処理す
ればＳｉ単結晶の表面近傍に結晶欠陥のないデヌーデッ
ドゾーンが形成される。デヌーデッドゾーンの厚さは熱
処理条件によって異なるが、１０〜ＩＱＯｐ鋼程度形成
され、表面に結晶欠陥が存在しない一方、結晶内部には
多数の結晶欠陥が作り出される。このようなデヌーデッ
ドゾーンに半導体デバイスを形成すると、結晶内部の結
晶欠陥が重金属などをゲッターするイントリンシックゲ
ッタリング（ｉｎｔｒｉｎｓｉｃ ｇｅｔｔｅｒｉｎｇ
）効果も相乗して、半導体素子の特性と製造歩留を著し
く向−トすることができる。Therefore, various methods have been proposed to remove such crystal defects.
After heat treatment at a relatively low temperature of 800℃ for several hours, and then returning to room temperature, a denuded zone with no crystal defects is created near the surface of the Si single crystal. The thickness of the denuded zone varies depending on the heat treatment conditions, but it is formed on the order of 10~IQOp steel, and while there are no crystal defects on the surface, many crystal defects are created inside the crystal. When a semiconductor device is formed in a denuded zone, intrinsic gettering occurs in which crystal defects inside the crystal getter heavy metals, etc.
) The effects can be combined to significantly improve the characteristics and manufacturing yield of semiconductor devices.
発明者らはこの様なデヌーデッドゾーンについて色々と
検討したところ、熱処理前に酸素濃度がＩ Ｘ １０”
、２以上含有されているＳｉ単結晶はデヌーデ、ドゾー
ンが形成されることが判り、又その熱処理方法も提案し
た。（特願昭５６−０２４００３他）本発明はかような
デヌーデッドゾーンを一層安定に且つ簡単に形成するこ
とを目的とするもので、その特徴は不活性ガス雰囲気中
で、６０（）〜８００℃。The inventors conducted various studies on such a denuded zone and found that the oxygen concentration before heat treatment was I x 10"
It has been found that denudes and dozones are formed in Si single crystals containing two or more of these, and a heat treatment method for this has also been proposed. (Japanese Patent Application No. 56-024003, etc.) The present invention aims to form such a denuded zone more stably and easily. 800℃.
２４時間以上の第１の熱処理を行ない、次いで商〜１１
００”、 ０．５時間以上の第２の熱処理を少くとも１
囲以上行ない、次いで１０００〜１２００℃、３時間以
上の第３の熱処理を行なうことにある製造方法で、以下
詳しく説明する。The first heat treatment is carried out for 24 hours or more, and then the
00”, a second heat treatment of 0.5 hours or more for at least 1
The manufacturing method is described in detail below, in which a third heat treatment is performed at 1000 to 1200° C. for 3 hours or more.
図表はデヌーデッドゾーンの形成と５１結晶中の酸素濃
度との関係を示しており、横軸は熱処理前の酸素濃度、
縦軸は熱処理後の酸素濃度減少量である。線ＩはＮｔガ
ス雰囲気中で７００℃、２４時間熱処理した後、常温に
戻し、次いで同じ雰囲気中で、１２００℃、３時間熱処
理したｉ−夕で、このような熱処理は前記したように既
に知られたものであるが、熱処理前の酸素濃度が１．Ｉ
Ｘ １０〜程度ではデヌーデ、ドゾーンは未だ形成さ
れなかった。The chart shows the relationship between the formation of the denuded zone and the oxygen concentration in 51 crystals, where the horizontal axis is the oxygen concentration before heat treatment,
The vertical axis is the amount of decrease in oxygen concentration after heat treatment. Line I shows heat treatment at 700°C for 24 hours in an Nt gas atmosphere, return to room temperature, and then heat treatment at 1200°C for 3 hours in the same atmosphere; as mentioned above, such heat treatment is already known. However, the oxygen concentration before heat treatment was 1. I
No denude or dezone was formed yet at X 10 or higher.
線■はＮ２ガス雰四気中で７００”＄ ２４時間熱処理
した後、常温に戻し、次いで９５０℃、０．５時間熱処
理して常温に戻し、次いで１２００℃、３時間熱処理し
たデータで、何れもＮ２ガス雰囲気中で熱処理するが、
図のように熱処理前の酸素濃度が１．０５ Ｘ １０曹
Ｍ程度で既にデヌーデッドゾーンが形成されている。Line (■) is data obtained by heat treatment at 700"$ for 24 hours in a N2 gas atmosphere, returning to room temperature, then heat treatment at 950℃ for 0.5 hours to return to room temperature, and then heat treatment at 1200℃ for 3 hours. is also heat treated in an N2 gas atmosphere,
As shown in the figure, a denuded zone has already been formed when the oxygen concentration before heat treatment is approximately 1.05 x 10 carbon dioxide.
線層は７００ｔ、 ２４時間熱処理した後、常温に戻し
、次いで９５０℃、０５時間熱処理して常温に戻し、更
に１１（Ｘ）Ｃ，０，５時間熱処理して常温に戻し、次
いで１２１ＸＦ、 ３時間熱処理したデータで、何れも
Ｎ、ガス雰囲気中であるが、この場合には熱処理前の酸
素濃度が１．ＯＸ １０〜程度の８１結晶もデヌーデッ
ドゾーンが形成され。したがって、本発明の第２の熱処
理として７００〜１１００℃の温度で比較的短時間行わ
れる熱処理の追加方法は酸素量が減少しやすくて安定し
たデヌーデッドゾーンが得られるものである。The wire layer was heat treated at 700t for 24 hours, then returned to room temperature, then heat treated at 950℃ for 0.5 hours to return to room temperature, further heat treated at 11(X)C for 0.5 hours to return to room temperature, then 121XF, 3 The data are for time heat treatment, both in N and gas atmospheres, but in this case the oxygen concentration before heat treatment was 1. A denuded zone was also formed in 81 crystals of OX 10 and above. Therefore, as the second heat treatment of the present invention, the method of adding heat treatment performed at a temperature of 700 to 1100° C. for a relatively short time is a method in which the amount of oxygen is easily reduced and a stable denuded zone can be obtained.
又、発明者らが繭紀Ｉｌ案した方法には、例えば第１の
熱処理を６００〜８００℃、１０時間以上、第２の熱処
理を１１５０〜１２５０℃、２時間以上、第３の熱処理
を９５０〜１０！５０℃、 １時間以上と同じく３−の
熱処理を行なってデス−デッドゾーンな形成する方法も
あるが、その場合は熱処理の雰囲気を非酸化性としたり
、酸化性としたりして甚だ雰囲気の制御が複雑であるが
、本発明は一貫としてＮ、ガスなどの不活性（非酸化性
）ガス雰囲気中で熱処理するから、その処理が非常に簡
単化される利点がある。In addition, the method proposed by the inventors includes, for example, a first heat treatment at 600 to 800°C for 10 hours or more, a second heat treatment at 1150 to 1250°C for 2 hours or more, and a third heat treatment at 950°C. ~10! There is also a method of forming a death zone by performing heat treatment at 50℃ for more than 1 hour to form a death zone, but in that case, the atmosphere for heat treatment may be non-oxidizing or oxidizing, causing severe damage. Although controlling the atmosphere is complicated, the present invention has the advantage that the heat treatment is performed in an atmosphere of an inert (non-oxidizing) gas such as N or gas, which greatly simplifies the process.
且つ、本発明において第３の熱処理条件は１０００〜１
２ｏＯ℃、３時間であるが、この＃＆理時間では厚さ８
０μ−のデヌーデッドゾーンが形成され、その地理時間
の長短によりその厚さを変えることが可能である。Moreover, in the present invention, the third heat treatment condition is 1000 to 1
The temperature is 2oO℃ for 3 hours, but the thickness is 8
A denuded zone of 0 μ- is formed, and its thickness can be changed depending on the length of the geographical time.
以上の説明から明らかなように、本発明はデヌーデッド
ゾーンが安定して簡単に形成で鯉、半導体装置の品質陶
土に極めて貢献するもので、その効果は大きい。As is clear from the above description, the present invention greatly contributes to the quality of chinaware for semiconductor devices by stably and easily forming a denuded zone, and its effects are significant.
図はデヌーデッドゾーンの形成有無を示すデータ図表で
ある。図中、線■は従来の熱処理条件、線■、線線層本
発明にかｈる熱処理条件で得たデータを示す。The figure is a data chart showing whether a denuded zone is formed or not. In the figure, line 2 indicates data obtained under conventional heat treatment conditions, and line 2 indicates data obtained under heat treatment conditions according to the present invention.
Claims (1)
不活性ガス雰囲気中（こおいて、温度６００〜ｓｏｏ℃
で、２４時間以上の第１熱処理を行ない、次いで温度７
００〜１１００℃で、３０分以上の第２熱処理を少なく
ともｌ回以上行ない、次いで温度１０００〜１２００″
Ｃで、３時間以上の第３の熱処理を行なう工程からなる
ことを特徴とする半導体装置の製造方法。When heat treating silicon crystal to form a defect-free layer,
In an inert gas atmosphere (temperature 600~soo℃)
Then, the first heat treatment was carried out for 24 hours or more, and then the temperature was increased to 7.
00 to 1100°C for 30 minutes or more at least 1 times, and then at a temperature of 1000 to 1200''
A method for manufacturing a semiconductor device, comprising the step of performing a third heat treatment for 3 hours or more in step C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11694881A JPS5818929A (en) | 1981-07-24 | 1981-07-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11694881A JPS5818929A (en) | 1981-07-24 | 1981-07-24 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5818929A true JPS5818929A (en) | 1983-02-03 |
| JPS639745B2 JPS639745B2 (en) | 1988-03-01 |
Family
ID=14699689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11694881A Granted JPS5818929A (en) | 1981-07-24 | 1981-07-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5818929A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4505759A (en) * | 1983-12-19 | 1985-03-19 | Mara William C O | Method for making a conductive silicon substrate by heat treatment of oxygenated and lightly doped silicon single crystals |
| US5506178A (en) * | 1992-12-25 | 1996-04-09 | Sony Corporation | Process for forming gate silicon oxide film for MOS transistors |
| WO2002049091A1 (en) | 2000-12-13 | 2002-06-20 | Shin-Etsu Handotai Co., Ltd. | Anneal wafer manufacturing method and anneal wafer |
| US7081422B2 (en) | 2000-12-13 | 2006-07-25 | Shin-Etsu Handotai Co., Ltd. | Manufacturing process for annealed wafer and annealed wafer |
| JP4615161B2 (en) * | 2001-08-23 | 2011-01-19 | 信越半導体株式会社 | Epitaxial wafer manufacturing method |
| JP2015164179A (en) * | 2014-01-29 | 2015-09-10 | 三菱マテリアル株式会社 | Electrode plate for plasma processing devices, and method for manufacturing the same |
-
1981
- 1981-07-24 JP JP11694881A patent/JPS5818929A/en active Granted
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4505759A (en) * | 1983-12-19 | 1985-03-19 | Mara William C O | Method for making a conductive silicon substrate by heat treatment of oxygenated and lightly doped silicon single crystals |
| US5506178A (en) * | 1992-12-25 | 1996-04-09 | Sony Corporation | Process for forming gate silicon oxide film for MOS transistors |
| WO2002049091A1 (en) | 2000-12-13 | 2002-06-20 | Shin-Etsu Handotai Co., Ltd. | Anneal wafer manufacturing method and anneal wafer |
| JP2002184779A (en) * | 2000-12-13 | 2002-06-28 | Shin Etsu Handotai Co Ltd | Annealed wafer and method of manufacturing the same |
| EP1343200A1 (en) * | 2000-12-13 | 2003-09-10 | Shin-Etsu Handotai Co., Ltd | Anneal wafer manufacturing method and anneal wafer |
| US7081422B2 (en) | 2000-12-13 | 2006-07-25 | Shin-Etsu Handotai Co., Ltd. | Manufacturing process for annealed wafer and annealed wafer |
| EP1343200A4 (en) * | 2000-12-13 | 2007-09-12 | Shinetsu Handotai Kk | Anneal wafer manufacturing method and anneal wafer |
| KR100847925B1 (en) | 2000-12-13 | 2008-07-22 | 신에츠 한도타이 가부시키가이샤 | Anneal wafer manufacturing method and anneal wafer |
| JP4615161B2 (en) * | 2001-08-23 | 2011-01-19 | 信越半導体株式会社 | Epitaxial wafer manufacturing method |
| JP2015164179A (en) * | 2014-01-29 | 2015-09-10 | 三菱マテリアル株式会社 | Electrode plate for plasma processing devices, and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS639745B2 (en) | 1988-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3022044B2 (en) | Method for manufacturing silicon wafer and silicon wafer | |
| JPS5818929A (en) | Manufacture of semiconductor device | |
| JPS63227026A (en) | Gettering method for silicon crystal substrate | |
| JPH09148336A (en) | Si semiconductor substrate and manufacturing method | |
| JPS60247935A (en) | Manufacture of semiconductor wafer | |
| JP3022045B2 (en) | Method of manufacturing silicon wafer and silicon wafer | |
| JPH0636979A (en) | Semiconductor device | |
| JP3294722B2 (en) | Method for manufacturing silicon wafer and silicon wafer | |
| JPS63198334A (en) | Manufacture of semiconductor silicon wafer | |
| JPS5994809A (en) | Production of semiconductor element | |
| JPH0897222A (en) | Manufacture of silicon wafer, and silicon wafer | |
| JPS6326541B2 (en) | ||
| JP2652346B2 (en) | Manufacturing method of silicon wafer | |
| JP2652344B2 (en) | Silicon wafer | |
| JPS624327A (en) | Manufacture of semiconductor device | |
| JP2588632B2 (en) | Oxygen precipitation method for silicon single crystal | |
| JPH0319687B2 (en) | ||
| JPH06291123A (en) | Fabrication of semiconductor device | |
| JPS6115335A (en) | Gettering method for silicon wafer | |
| JPS58116741A (en) | Manufacture of semiconductor device | |
| JPH04276627A (en) | Semiconductor device production method | |
| JPS594128A (en) | Manufacture of semiconductor device | |
| JPH05283350A (en) | Manufacture of epitaxial semiconductor wafer | |
| JPS61168599A (en) | Method of purifying silicon wafer | |
| JPS58170020A (en) | Manufacture of semiconductor device |