JPS58182242U - スライドロツク付プツシユボタン - Google Patents

スライドロツク付プツシユボタン

Info

Publication number
JPS58182242U
JPS58182242U JP7870482U JP7870482U JPS58182242U JP S58182242 U JPS58182242 U JP S58182242U JP 7870482 U JP7870482 U JP 7870482U JP 7870482 U JP7870482 U JP 7870482U JP S58182242 U JPS58182242 U JP S58182242U
Authority
JP
Japan
Prior art keywords
button
protrusion
slide lock
recess
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7870482U
Other languages
English (en)
Inventor
寺田　龍平
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP7870482U priority Critical patent/JPS58182242U/ja
Publication of JPS58182242U publication Critical patent/JPS58182242U/ja
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図はこの考案のスライドロック付ブツシュ−ボタン
の一実施例のノンロック時の状態を示す断面図、第２図
は同上スライドロック付ブツシュボタンのロック時の状
態を示す断面図である。−１・・・・・・ケース、１ａ
・・・・・・孔、１ｂ・・・・・・凹部、ｌｃ。 １ｄ・・・・・・段部、２・・・ボタン、４・・・アー
ム、４ａ。 ４ｂ・・・・・・突起、５・・・・・・板ばね、７・・
・・・・スイッチ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 内面に凹部および段部を有するケースと、このケースに
    遊挿され、ケースの前面に突出されたボタンと、このボ
    タンと一体的に形成されてノンロック時に上記凹部に係
    合する突起を有しノンロック時に上記ボタンを押すとこ
    の突起を支点として回動し、かつロック時に上記ボタン
    を押圧してスライドさせることにより上記突起が上記凹
    部から離脱するとともに、上記段部に係止されるアーム
    と、上記ノンロック時に上記ボタンの押圧力を解除する
    と、上記アームの回動を元に戻すばねとよ　−りなるス
    ライドロ；ンク付ブツシュボタン。
JP7870482U 1982-05-28 1982-05-28 スライドロツク付プツシユボタン Pending JPS58182242U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7870482U JPS58182242U (ja) 1982-05-28 1982-05-28 スライドロツク付プツシユボタン

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7870482U JPS58182242U (ja) 1982-05-28 1982-05-28 スライドロツク付プツシユボタン

Publications (1)

Publication Number Publication Date
JPS58182242U true JPS58182242U (ja) 1983-12-05

Family

ID=30087908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7870482U Pending JPS58182242U (ja) 1982-05-28 1982-05-28 スライドロツク付プツシユボタン

Country Status (1)

Country Link
JP (1) JPS58182242U (ja)

Cited By (17)

* Cited by examiner, † Cited by third party
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US8836045B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US8921896B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit including linear gate electrode structures having different extension distances beyond contact
US8951916B2 (en) 2007-12-13 2015-02-10 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8966424B2 (en) 2007-03-07 2015-02-24 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9202779B2 (en) 2008-01-31 2015-12-01 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9240413B2 (en) 2006-03-09 2016-01-19 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9269702B2 (en) 2009-10-13 2016-02-23 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the same
US9336344B2 (en) 2006-03-09 2016-05-10 Tela Innovations, Inc. Coarse grid design methods and structures
US9390215B2 (en) 2008-03-27 2016-07-12 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9595515B2 (en) 2007-03-07 2017-03-14 Tela Innovations, Inc. Semiconductor chip including integrated circuit defined within dynamic array section

Cited By (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9425145B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9425273B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9425272B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same
US9240413B2 (en) 2006-03-09 2016-01-19 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9589091B2 (en) 2006-03-09 2017-03-07 Tela Innovations, Inc. Scalable meta-data objects
US9336344B2 (en) 2006-03-09 2016-05-10 Tela Innovations, Inc. Coarse grid design methods and structures
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8921896B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit including linear gate electrode structures having different extension distances beyond contact
US8921897B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit with gate electrode conductive structures having offset ends
US8946781B2 (en) 2006-03-09 2015-02-03 Tela Innovations, Inc. Integrated circuit including gate electrode conductive structures with different extension distances beyond contact
US9443947B2 (en) 2006-03-09 2016-09-13 Tela Innovations, Inc. Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same
US8952425B2 (en) 2006-03-09 2015-02-10 Tela Innovations, Inc. Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length
US8966424B2 (en) 2007-03-07 2015-02-24 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9595515B2 (en) 2007-03-07 2017-03-14 Tela Innovations, Inc. Semiconductor chip including integrated circuit defined within dynamic array section
US9424387B2 (en) 2007-03-07 2016-08-23 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8951916B2 (en) 2007-12-13 2015-02-10 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9281371B2 (en) 2007-12-13 2016-03-08 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9530734B2 (en) 2008-01-31 2016-12-27 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9202779B2 (en) 2008-01-31 2015-12-01 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8872283B2 (en) 2008-03-13 2014-10-28 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
US9213792B2 (en) 2008-03-13 2015-12-15 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US9208279B2 (en) 2008-03-13 2015-12-08 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods
US9536899B2 (en) 2008-03-13 2017-01-03 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US9245081B2 (en) 2008-03-13 2016-01-26 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US8853793B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
US8847331B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
US8866197B2 (en) 2008-03-13 2014-10-21 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature
US8836045B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
US8853794B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit within semiconductor chip including cross-coupled transistor configuration
US9117050B2 (en) 2008-03-13 2015-08-25 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
US8847329B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts
US8835989B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications
US9390215B2 (en) 2008-03-27 2016-07-12 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US9530795B2 (en) 2009-10-13 2016-12-27 Tela Innovations, Inc. Methods for cell boundary encroachment and semiconductor devices implementing the same
US9269702B2 (en) 2009-10-13 2016-02-23 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same

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