JPS58175856A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS58175856A JPS58175856A JP5918282A JP5918282A JPS58175856A JP S58175856 A JPS58175856 A JP S58175856A JP 5918282 A JP5918282 A JP 5918282A JP 5918282 A JP5918282 A JP 5918282A JP S58175856 A JPS58175856 A JP S58175856A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- collector
- input
- transistor
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 230000010354 integration Effects 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体集積回路装置に係り、特にエミッタ結
合論理（ｍｃＬ）回路のベース入力保護回路の構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of a base input protection circuit of an emitter-coupled logic (mcL) circuit.
第１図は従来のＫＣＬ回路の回路構成図で、Ｔｌ。FIG. 1 is a circuit diagram of a conventional KCL circuit.
７２Ｆｉエミツタを共通接続されたｎｐｎ ）ランジス
タ、Ｒ】およびＲ３ＦｉそれぞれトランジスタＴ１おｊ
びＴｌのコレクタ負荷抵抗、Ｒ３は両トランジスタＴｌ
、 Ｔｌの共通エミッタ抵抗、Ｔ３はトランジスタＴ２
のコレクタにペースが接続されたエミッタホロアトラン
ジスタ、Ｒ＜ｕそのエミッタ抵抗で入力端チェ）Ｊ＃ｉ
）ランジスタＴＩのペースに、出ヵ端子ＯＵＴはエミッ
タホロアトランジスタＴ３のエミッタに接続され、トラ
ンジスタＴ２のペースには基準電圧Ｖｌｌが供給される
。ＶＣＣはコレクタ側電源、ｖＫＦｉはエミッタ側電源
である。そして、この従来回路では入力端子ＩＮとエミ
ッタ側電源ｖｍｍとの間に入力保饅ダイオードＤｌが設
けられている。72Fi emitters commonly connected npn) transistor, R] and R3Fi transistor T1 and
and collector load resistance of both transistors Tl, R3 is the collector load resistance of both transistors Tl
, the common emitter resistance of Tl, T3 is the transistor T2
An emitter-follower transistor with a pace connected to the collector of the input terminal (R<u) with its emitter resistance
) The output terminal OUT is connected to the emitter of the emitter-follower transistor T3 to the base of the transistor TI, and the reference voltage Vll is supplied to the base of the transistor T2. VCC is a collector side power supply, and vKFi is an emitter side power supply. In this conventional circuit, an input protection diode Dl is provided between the input terminal IN and the emitter side power supply vmm.
保腫ダイオードＤ１のないＩＣｏＬ回路では、入力ｍチ
ェＮへの正極性パルスはトランジスタＴ１のペース・エ
ミッタ間接合に対して順方向であるので、その順方向電
圧降下（ＩＶ以下）を生ぜしめるに過ぎないが、負極性
のパルスは上記接合にアバランシ降伏を生じさせ、その
降伏電圧は約５ｖであるので、接合で消費される電力は
正極性の場合に比してはるかに大きく、発熱による素子
破壊へとつながる。これを防止するために、第１図の回
路では負極性のパルスが入力ＩＮへ加わったとき、これ
を短絡してそのパルス電圧がトランジスタＴ１のペース
に印加されないようにするために保論ダイオードＤ１が
設けられており、これによって、負極性入力パルスに対
する破壊耐量を正極性入力パルスに対する値程度になる
ようにしている。In the ICoL circuit without the occlusion diode D1, the positive pulse to the input mcheN is in the forward direction with respect to the pace-emitter junction of the transistor T1, so that the forward voltage drop (less than IV) will occur. However, the negative polarity pulse causes avalanche breakdown in the junction, and the breakdown voltage is about 5V, so the power consumed in the junction is much larger than in the case of positive polarity, and the element heats up. leading to destruction. To prevent this, when a negative pulse is applied to the input IN in the circuit of FIG. is provided, thereby making the breakdown resistance against negative input pulses approximately equal to the value for positive input pulses.
第２図は第１図の従来回路を集積回路化したときの、特
に破線で囲−んだＡ部のパターン概略配置図で、ＴＩ＋
Ｔ、！＋ Ｒ３およびＤ】で示したのはそれぞれトラ
ンジスタＴ１＋ Ｔ２＋抵抗Ｒ３および保護夕゛イオー
ドＤＪの形成領域を示し、■は各素子形成領域間の分離
拡散領域である。Figure 2 is a schematic layout diagram of the pattern of part A, which is surrounded by a broken line, when the conventional circuit in Figure 1 is integrated.
T,! +R3 and D] indicate the formation regions of the transistors T1+T2+resistance R3 and the protective diode DJ, respectively, and .largecircle. is the isolation diffusion region between each element formation region.
このように従来の回路方式では保瑣ダイオードＤｌｆ、
ＫＣＬ構成素子の形成領域とは分離した領域に形成せね
ばならず、回路の集積度を低下させる欠点があった。In this way, in the conventional circuit system, the protection diode Dlf,
It has to be formed in a region separate from the formation region of the KCL component, which has the disadvantage of lowering the degree of circuit integration.
この発明は以上のような点に鑑みてなされたもので、入
力保饅用素子をトランジスタで構成することによって、
これをエミッタ結合トランジスタ回路の構成素子と四−
形成領域内に形成できるようにし、集積度を低下させる
ことなく入カ保峡機能を達成することを目的としている
。This invention was made in view of the above points, and by configuring the input protection element with a transistor,
This is called a component of an emitter-coupled transistor circuit.
The purpose of this is to enable the formation within the formation area and to achieve the input hole function without reducing the degree of integration.
ｆｊｐＪ３図はこの発明の一実施例のＥＯＬ回路の回路
構成図で、第１図の従来例と同等部分は同一符号で示し
、その説明の重複は避ける。Ｔ４はエミッタが入力端子
１Ｎに、ペースがトランジスタＴＩのエミッタに、コレ
クタがコレクタ側電源Ｖｃｃ、に接続された入力保賎用
ｎｐｎ ）ランジスタで、従来例のダイオードＤ１と同
様に、トランジスタＴ１がアバランシ降伏するのを防止
する。Fig. fjpJ3 is a circuit configuration diagram of an EOL circuit according to an embodiment of the present invention. Portions equivalent to those of the conventional example of Fig. 1 are designated by the same reference numerals to avoid duplication of explanation. T4 is an input protection npn transistor whose emitter is connected to the input terminal 1N, whose pace is connected to the emitter of the transistor TI, and whose collector is connected to the collector side power supply Vcc.Similar to the conventional diode D1, the transistor T1 is connected to the avalanche Prevent surrender.
第４図は第３図の回路を集積回路化したと色の、特に破
線で囲んだＡ部のパターン概略配置図、第５図（ａ）は
トランジスタＴ４と抵抗Ｒ３との形成領域のみの具体的
パターン構成図、第５図（ｂ）は第６図（ａ）のＶＢ−
ＶＢ線での断面図である。図において、（１）Ｖｉｐ形
基板基板２）はｎ形堀込層、（３）はその上に形成され
たｎ形エピタキシャル成長層、（４）はｎ形エピタキシ
ャル成長層（３）の一部に形成されたｐ形拡散膚、（６
）はｐ形波散層（４）の表面部の一部に形成されたｎ形
拡散領域、（６）は表面絶縁膜で、トランジスタＴ４は
ｎ形エピタキシャル成長層（３）ヲコレクタ、ｐ形波散
層（４）をペース、ｎ形拡散領域（６）をエミッタとし
て構成され、ｐ形拡散層＋４）＃′ｉ第５図（−）に示
すように長く延ｒＩ：て抵抗Ｒ３’に構成している。（
７）は表面絶縁膜（６）全貫通してｎ形拡散領域（６）
に接続するトランジスタＴ４のエミッタ配線、（８）は
表面絶縁膜ｔｅｌに設けられたコンタクト孔（９）を介
してｐ形波散層（４）に接続するトランジスタＴ４のペ
ース配線である。第３図のＲＣＬ回路を構成するにはｐ
形基板口）ｉｉミニミッタ電源ｖＥＥに、ｎ形埋込層（
２）およびｎｉエピタキシャル成長層（３）はコレクタ
側電源ＶＣＣに接続される。従って、８ｉ！３図に示す
ような保護用トランジスタＴａｔ抵抗Ｒ３の形成ｐ影領
域（４）内＆Ｌ ｎ形拡散領域（６）を設けるだけで構
成でき、従来装置に比して集積度を向上できる。FIG. 4 is a schematic layout diagram of the pattern of part A surrounded by a broken line, especially when the circuit of FIG. 3 is integrated into an integrated circuit, and FIG. Fig. 5(b) is the VB- pattern configuration diagram of Fig. 6(a).
It is a sectional view taken along the VB line. In the figure, (1) Vip type substrate 2) is an n-type digging layer, (3) is an n-type epitaxial growth layer formed thereon, and (4) is a part of the n-type epitaxial growth layer (3). p-type diffuse skin, (6
) is an n-type diffusion region formed on a part of the surface of the p-type wave dispersion layer (4), (6) is a surface insulating film, and transistor T4 is a collector of the n-type epitaxial growth layer (3), and a p-type wave dispersion layer (3). The layer (4) is used as a paste, the n-type diffusion region (6) is used as an emitter, and the p-type diffusion layer +4) #'i is extended as shown in FIG. 5 (-) to form a resistor R3'. ing. (
7) is the n-type diffusion region (6) that completely penetrates the surface insulating film (6)
(8) is a pace wiring of the transistor T4 connected to the p-type dispersion layer (4) through a contact hole (9) provided in the surface insulating film tel. To configure the RCL circuit shown in Figure 3, p
type board opening) ii minimitter power supply vEE, n type buried layer (
2) and the ni epitaxial growth layer (3) are connected to the collector side power supply VCC. Therefore, 8i! The protective transistor Tat resistance R3 can be formed by simply providing an n-type diffusion region (6) in the p-shade region (4) as shown in FIG. 3, and the degree of integration can be improved compared to the conventional device.
なお、上ｌｉｄ説明ではすべてｎｐｎ トランジスタで
構成した場合を示したがｐｎｐ ）ランジスタの場合は
各部の半導体の伝導形を反転させればよいことは勿論で
ある。In the above description, the case is shown in which everything is composed of npn transistors, but in the case of pnp (pnp) transistors, it goes without saying that the conduction type of the semiconductor in each part may be reversed.
以上説明したように、この発明では集積回路構成のＫＯ
Ｌ回路の共通エミッタ抵抗を形成する拡散層の表面部の
一部にこれと異なる伝導形を有する拡散領域を形成し、
この拡散領域をエミッタとし上記拡散層ｔペースとし、
この拡散Ｍを囲みＥＣＬ回路のコレクタ側電源に接続さ
れた半導体屑をコレクタとするトランジスタを構成せし
め、これを入力保護用として用いたので、入力保護用素
子用として別個の形成領域を必要とせず回路集積度を高
く保つことがで睡る。As explained above, in the present invention, the KO
A diffusion region having a conductivity type different from that of the diffusion layer is formed in a part of the surface portion of the diffusion layer forming the common emitter resistance of the L circuit,
This diffusion region is used as an emitter, and the diffusion layer t is used as a pace,
A transistor whose collector is a semiconductor chip surrounding this diffusion M and connected to the collector side power supply of the ECL circuit is constructed, and this is used for input protection, so there is no need for a separate formation area for an input protection element. This is achieved by keeping the circuit density high.
８ｇ１図は従来のＦ、Ｃ１１回路の回路構成図、第２図
はＩ４１図の従来回路を集積回路化したと色の特にＡ部
のパターン概略配置図、８Ｉ３図はこの発明の一実施例
のＥＯＬ回路の回路構成図、第４図はこれを集積回路化
したと色の、特にＡ部のパターン概略配置図、第５図（
ａ）はトランジスタＴ４と抵抗Ｆ３との形成領域のみの
具体的パターン構成図、第５図（１））Ｆｉｌ＠５図（
ａ）のＶＢ −ＶＢ 線での断面図である。
図において、Ｔ１＋ ＴＦＩｄ、共通エミッタ接続のト
ランジスタ、ＲＩ＋ Ｒ２ＦＡコレクタ抵抗、Ｒ３ハ共
通エミッタ抵抗、ＩＮは入力端子、ｖＢＩｌは基準電圧
源、ｖｌｍはエミッタ側電源、ＶＣＣけコレクタ側電源
、Ｔ４は保護用（付加）トランジスタ、（３１に′ｉエ
ピタキシャル成長ｍ（半導体層） 、＋４１は拡散層、
（６）は拡散領域である。
なお、図中同一符号は同一または相当部分を示す０
代理人 葛 野 信 −（外１名）
第１図
第２１４
第３ ｒ２１
第ｒ）図Figure 8g1 is a circuit configuration diagram of the conventional F and C11 circuits, Figure 2 is a schematic layout diagram of the pattern of part A, especially the part A, which is an integrated circuit of the conventional circuit in Figure I41, and Figure 8I3 is a diagram of an embodiment of the present invention. The circuit configuration diagram of the EOL circuit, Figure 4, is a schematic diagram of the pattern layout of part A, especially when it is integrated into an integrated circuit, and Figure 5 (
a) is a specific pattern configuration diagram of only the formation area of transistor T4 and resistor F3, FIG. 5(1)) Fil@FIG.
It is a sectional view taken along the line VB-VB of a). In the figure, T1+ TFId, transistor with common emitter connection, RI+ R2FA collector resistance, R3 C common emitter resistance, IN is input terminal, vBIl is reference voltage source, vlm is emitter side power supply, VCC is collector side power supply, T4 is for protection (Additional) transistor, (31 is epitaxial growth m (semiconductor layer), +41 is a diffusion layer,
(6) is a diffusion region. In addition, the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
もに一方のペースが入力端子に接続され、他方のペース
に基準電圧が供給される２つのトランジスタ、上記共通
に接続されたエミッタとエミッタ側１１源との間に接続
された共通エミッタ抵抗、および上記２つのトランジス
タのそれぞれのコレクタとコレクタ側電源との間に接続
されたコレクタ抵抗を備え、上記２つのトランジスタの
コレクタからそれぞれ上記入力端子へ供給される入力信
号の反転信号、および非反転信号を得られるようにした
エミッタ結合論理回路が形成された半導体集積回路装置
において、正（または負）極性の上記コレクタ側電源が
接続されるｎ（またｔｉｐ）形の半導体層内に形成され
上記共通エミッタ抵抗を構成するｐ（またはｎ）形波散
層の表面部の一部にｎ（またはｐ）形拡散領域を設け、
上記ｎ（ｔたｕｐ）形拡散領域をエミッタ、上記ｐ（ま
たはｎ）形波散層をペース、上記ｎ（またはｐ）形の半
導体層をコレクタとする付加トランジスタを構成せしめ
、上記付加トランジスタのエミッタを上記入力端子に接
続して上記付加トランジスタに上記エミッタ結合論理回
路の入カ保験の機能をもたせ □るようＫしたこと
′に特徴とする半導体集積回路装置。fil two transistors whose emitters are connected in common, one pace is connected to the input terminal, and the other pace is supplied with a reference voltage, the emitters connected in common and the emitter side 11 source a common emitter resistor connected between the transistors, and a collector resistor connected between the collectors of the two transistors and a collector-side power supply, each of which is supplied from the collectors of the two transistors to the input terminal. In a semiconductor integrated circuit device in which an emitter-coupled logic circuit is formed that can obtain an inverted signal and a non-inverted signal of an input signal, the collector side power supply of positive (or negative) polarity is connected to the ) type semiconductor layer and forming an n (or p) type diffusion region in a part of the surface portion of the p (or n) type wave diffusion layer constituting the common emitter resistance,
An additional transistor is constructed in which the n (tup) type diffusion region is an emitter, the p (or n) type wave diffusion layer is a base, and the n (or p) type semiconductor layer is a collector. A semiconductor integrated circuit device characterized in that an emitter is connected to the input terminal so that the additional transistor has an input guarantee function for the emitter-coupled logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5918282A JPS58175856A (en) | 1982-04-07 | 1982-04-07 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5918282A JPS58175856A (en) | 1982-04-07 | 1982-04-07 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58175856A true JPS58175856A (en) | 1983-10-15 |
Family
ID=13106003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5918282A Pending JPS58175856A (en) | 1982-04-07 | 1982-04-07 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58175856A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58207722A (en) * | 1982-05-28 | 1983-12-03 | Nec Corp | Logical circuit |
| JPS5912626A (en) * | 1982-07-13 | 1984-01-23 | Nec Corp | Current switching type logical circuit |
-
1982
- 1982-04-07 JP JP5918282A patent/JPS58175856A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58207722A (en) * | 1982-05-28 | 1983-12-03 | Nec Corp | Logical circuit |
| JPH0261819B2 (en) * | 1982-05-28 | 1990-12-21 | Nippon Electric Co | |
| JPS5912626A (en) * | 1982-07-13 | 1984-01-23 | Nec Corp | Current switching type logical circuit |
| JPH0261820B2 (en) * | 1982-07-13 | 1990-12-21 | Nippon Electric Co |
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