JPS5817569U - Digital integrated circuit measurement equipment - Google Patents

Digital integrated circuit measurement equipment

Info

Publication number
JPS5817569U
JPS5817569U JP11125681U JP11125681U JPS5817569U JP S5817569 U JPS5817569 U JP S5817569U JP 11125681 U JP11125681 U JP 11125681U JP 11125681 U JP11125681 U JP 11125681U JP S5817569 U JPS5817569 U JP S5817569U
Authority
JP
Japan
Prior art keywords
integrated circuit
digital integrated
input terminal
measurement equipment
circuit measurement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11125681U
Other languages
Japanese (ja)
Other versions
JPS631247Y2 (en
Inventor
豊 脇
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP11125681U priority Critical patent/JPS5817569U/en
Publication of JPS5817569U publication Critical patent/JPS5817569U/en
Application granted granted Critical
Publication of JPS631247Y2 publication Critical patent/JPS631247Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例であるディジタル集積回路測
定装置のブロック図である。第２図は本考案の動作原理
を説明するためのタイムチャートである。 尚、図において、１・・・・・・試料、２・・・・・・
電源、３・・・・・・電流計測器、４・・・・・・ピー
ク電り検知器、５・・・・・・ファンクションジェネレ
ータ、６・・・・・・カウンタ、７・・・・・・メモリ
、８，９・・・・・・試料の電源端子、１０・・・・・
・試料の信号入力端子群、１１・・・・・・試料の出力
端子群、Ｉｒｘ・・・・・・消費電流、石′・・・・・
・真の消費電流、ｔ・・・・・・時間、である。FIG. 1 is a block diagram of a digital integrated circuit measuring device which is an embodiment of the present invention. FIG. 2 is a time chart for explaining the operating principle of the present invention. In addition, in the figure, 1...sample, 2...
Power supply, 3...Current measuring device, 4...Peak electricity detector, 5...Function generator, 6...Counter, 7... ...Memory, 8, 9... Sample power supply terminal, 10...
- Sample signal input terminal group, 11... Sample output terminal group, Irx... Current consumption, Stone'...
-True current consumption, t...time.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ディジタル集積回路の信号入力端子に任意の入力バイア
スを与えて電源入力端子に流入する電流を測定するディ
ジタル集積回路の消費電流測定装置において、前記電源
入力端子に流入する電流が最大となる信号入力端子の入
力バイアス条件を検知し、前記入力バイアス条件を固定
して消費−流の最大値を測定することを特徴とするディ
ジタル集積回路測定装置。In a current consumption measurement device for a digital integrated circuit that applies an arbitrary input bias to the signal input terminal of a digital integrated circuit and measures the current flowing into the power input terminal, the signal input terminal at which the current flowing into the power input terminal is maximum. 1. A digital integrated circuit measuring device, comprising: detecting an input bias condition, and measuring a maximum value of current consumption while fixing the input bias condition.
JP11125681U 1981-07-27 1981-07-27 Digital integrated circuit measurement equipment Granted JPS5817569U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11125681U JPS5817569U (en) 1981-07-27 1981-07-27 Digital integrated circuit measurement equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11125681U JPS5817569U (en) 1981-07-27 1981-07-27 Digital integrated circuit measurement equipment

Publications (2)

Publication Number Publication Date
JPS5817569U true JPS5817569U (en) 1983-02-03
JPS631247Y2 JPS631247Y2 (en) 1988-01-13

Family

ID=29905595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11125681U Granted JPS5817569U (en) 1981-07-27 1981-07-27 Digital integrated circuit measurement equipment

Country Status (1)

Country Link
JP (1) JPS5817569U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50159270A (en) * 1974-06-12 1975-12-23

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50159270A (en) * 1974-06-12 1975-12-23

Also Published As

Publication number Publication date
JPS631247Y2 (en) 1988-01-13

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