JPS58159700U - Memory data protection circuit - Google Patents

Memory data protection circuit

Info

Publication number
JPS58159700U
JPS58159700U JP10234282U JP10234282U JPS58159700U JP S58159700 U JPS58159700 U JP S58159700U JP 10234282 U JP10234282 U JP 10234282U JP 10234282 U JP10234282 U JP 10234282U JP S58159700 U JPS58159700 U JP S58159700U
Authority
JP
Japan
Prior art keywords
semiconductor memory
protection circuit
detector
output
data protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10234282U
Other languages
Japanese (ja)
Other versions
JPS6117476Y2 (en
Inventor
小柳 智生
内海 浄
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP10234282U priority Critical patent/JPS58159700U/en
Publication of JPS58159700U publication Critical patent/JPS58159700U/en
Application granted granted Critical
Publication of JPS6117476Y2 publication Critical patent/JPS6117476Y2/ja
Granted legal-status Critical Current

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  • Power Sources (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Stand-By Power Supply Arrangements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示すブロック図、第2図はそ
の一部の回路図である。 図面で1はメモリ、2は制御回路、3は電源、4はバッ
テリ、7.9はゲート回路である。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a partial circuit diagram thereof. In the drawing, 1 is a memory, 2 is a control circuit, 3 is a power supply, 4 is a battery, and 7.9 is a gate circuit.

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)装置電源の遮断時に引続いて電力を供給するバッ
テリを付設された半導体メモリの記憶データ保護回路に
おいて、入力データより特定のデータを検出する検出器
と、書込み命令が半導体メモリへ入力するのを該検出器
の出力に応じて′#JII御するゲート回路を備え、該
ゲート回路はメモリへのデータ書込みに際して送出され
る第1の特定のデータを検出した前記検出器の出力によ
り書込み命令通過可能状態となり、また書込み終了で送
出される第2の特定のデータを検出した前記検出器出力
で書込み命令通過不可状態となることを特徴とする半導
体メモリの記憶データ保護回路。
(1) In the storage data protection circuit of the semiconductor memory, which is equipped with a battery that continues to supply power when the device power is cut off, there is a detector that detects specific data from input data, and a write command is input to the semiconductor memory. The gate circuit is provided with a gate circuit that controls the output of the detector according to the output of the detector, and the gate circuit issues a write command based on the output of the detector that has detected the first specific data sent when writing data to the memory. 1. A storage data protection circuit for a semiconductor memory, wherein the storage data protection circuit for a semiconductor memory enters a state in which it is possible to pass, and becomes in a state in which it is not possible to pass a write command at the output of the detector that detects second specific data sent at the end of writing.
(2)特定のデータが、半導体メモリへ書込まれる入力
データのビット数と同じビット数のコードの1組または
複数組で構成されることを特徴とする実用新案登録請求
の範囲第1項記載の半導体メモリの記憶データ保護回路
(2) Claim 1 of the Utility Model Registration Claim characterized in that the specific data is composed of one or more sets of codes having the same number of bits as the number of bits of the input data written into the semiconductor memory. storage data protection circuit for semiconductor memory.
(3)ゲート回路が記憶素子および該素子の出力とクロ
ックとを入力とするアンドゲートからなり、該記憶素子
への特定のデータの書込みが該特定のデータのサンプル
クロックにより行なわれることを特徴とした実用新案登
録請求の範囲第1項または第2項記載の半導体メモリの
記憶データ保護回路。
(3) The gate circuit comprises a memory element and an AND gate that receives the output of the element and a clock as inputs, and writing of specific data to the memory element is performed using a sample clock of the specific data. A storage data protection circuit for a semiconductor memory according to claim 1 or 2 of the registered utility model claim.
JP10234282U 1982-07-06 1982-07-06 Memory data protection circuit Granted JPS58159700U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10234282U JPS58159700U (en) 1982-07-06 1982-07-06 Memory data protection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10234282U JPS58159700U (en) 1982-07-06 1982-07-06 Memory data protection circuit

Publications (2)

Publication Number Publication Date
JPS58159700U true JPS58159700U (en) 1983-10-24
JPS6117476Y2 JPS6117476Y2 (en) 1986-05-28

Family

ID=30101086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10234282U Granted JPS58159700U (en) 1982-07-06 1982-07-06 Memory data protection circuit

Country Status (1)

Country Link
JP (1) JPS58159700U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50159637A (en) * 1974-06-12 1975-12-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50159637A (en) * 1974-06-12 1975-12-24

Also Published As

Publication number Publication date
JPS6117476Y2 (en) 1986-05-28

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