JPS58158970A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58158970A JPS58158970A JP4105982A JP4105982A JPS58158970A JP S58158970 A JPS58158970 A JP S58158970A JP 4105982 A JP4105982 A JP 4105982A JP 4105982 A JP4105982 A JP 4105982A JP S58158970 A JPS58158970 A JP S58158970A
- Authority
- JP
- Japan
- Prior art keywords
- source
- gate electrode
- drain regions
- region
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 239000002131 composite material Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 230000005669 field effect Effects 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 25
- 229910021332 silicide Inorganic materials 0.000 abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- 230000001590 oxidative effect Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 235000012054 meals Nutrition 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、Ｍ０８型電界効果半導体装置の高速性と信頼
性を向上する技術に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technique for improving the high speed and reliability of an M08 field effect semiconductor device.
第１図に、ゲート電極に多結晶シリコンと金属とシリコ
ンの合金層（以下シリサイドと称する）との複合膜構造
を有するＭＯａ型電界効果半導体＃ｉ＆置装従来の製造
方法を示す。FIG. 1 shows a conventional manufacturing method for an MOa field effect semiconductor #i & device having a gate electrode having a composite film structure of polycrystalline silicon and an alloy layer of metal and silicon (hereinafter referred to as silicide).
半導体基体（１）の表面を公知の選択酸化法によシ厚い
フィールド絶縁膜（２）及び薄いゲート絶縁膜（３）を
形成した後、多結晶シリコンよυなるゲート電極（４）
を形成し、ゲート電極（４）をマスクとしてソース、ド
レイン領域（５，６）をイオン注入法又は高温拡散法に
よ如形成する。（第１図−１））次いでゲート電極（４
）の表面にシリサイド層（７）を形成する。シリサイド
層（７）は例えば金属を蒸着した後に熱Ｉ＆堤を行い、
シリサイド層（７）以外の部分の金属をエツチング除去
して形成することができる。（第１図−ｂ））
次いで気相成長絶縁膜（８）を形成した後、ソース。After forming a thick field insulating film (2) and a thin gate insulating film (3) on the surface of the semiconductor substrate (1) by a known selective oxidation method, a gate electrode (4) made of polycrystalline silicon is formed.
, and using the gate electrode (4) as a mask, source and drain regions (5, 6) are formed by ion implantation or high temperature diffusion. (Figure 1-1)) Next, the gate electrode (4)
) A silicide layer (7) is formed on the surface of the silicide layer (7). The silicide layer (7) is formed by, for example, performing thermal I&D after depositing a metal.
It can be formed by etching away the metal other than the silicide layer (7). (FIG. 1-b)) Next, after forming a vapor phase growth insulating film (8), a source is formed.
ドレイン領域（５，６）に達するスルーホール（９，１
０）を開孔し、（第１図−〇））次いで金属配線層（１
１゜１２）を形成して半導体装置を完成する。Through holes (9, 1) reaching drain regions (5, 6)
0) is opened (Fig. 1-〇)), and then a metal wiring layer (1) is formed.
1°12) is formed to complete the semiconductor device.
又、８２図に浅いソース、ドレイン拡散領域を有するＭ
Ｏ８型電界効果半導体装皺０従来の製造方法を示す。半
導体基体（２０）の表面にフィールド絶縁ＩＩ（２１）
、ゲート絶縁膜（２２）を形成し、次いで多結晶シリコ
ンによるゲート電＆（２３）を形成した後１例えばヒ素
をイオン注入することによシ、ソース、ドレイン領域（
２４、２５）を形成し、表面を気相成長絶縁Ｍｌ（２６
）で覆う。（第２図−ｍ））次いでソース、ドレイン領
域に達するスルーホール（２７，２８）を開孔し、続い
てスルーホール（２７゜２８）Ｋよ妙手導体基体（２０
）表面が無比した領域Ｋ。Also, in Fig. 82, M with shallow source and drain diffusion regions is shown.
A conventional manufacturing method for an O8 type field effect semiconductor device is shown. Field insulation II (21) on the surface of the semiconductor substrate (20)
After forming a gate insulating film (22) and then forming a gate electrode (23) of polycrystalline silicon, the source and drain regions (1) are formed by ion-implanting, for example, arsenic.
24, 25), and the surface is coated with vapor phase growth insulation Ml (26
). (Fig. 2-m)) Next, through holes (27, 28) reaching the source and drain regions are opened, and then the through holes (27°28) K and the fine conductor substrate (20
) Area K with an unparalleled surface.
例えばリンを拡散し、ソース、ドレイン領域（２４゜２
５）よりｓい拡散領域（２９，３０）を形成する。（第
２図＝ｂ））
次いで金属配線層（３１，３２）を形成して、半導体装
置を完成する。For example, by diffusing phosphorus into the source and drain regions (24°2
5) Forming narrower diffusion regions (29, 30). (FIG. 2 = b)) Next, metal wiring layers (31, 32) are formed to complete the semiconductor device.
第１図に示す多結晶シリコンとシリサイドの複合膜によ
るゲート電極を有する半導体装を社ゲート電極の抵抗が
多結晶シリ；ンのみをゲート電極材料とする場合と比較
して約１ケタ〜２ケタ小さい為、ゲート電極内、又はゲ
ート電極と同材料による配ＩＩ！１１内での信号の遅れ
が小さく、装置の高速動作に効果があった。In a semiconductor device having a gate electrode made of a composite film of polycrystalline silicon and silicide as shown in Fig. 1, the resistance of the gate electrode is approximately 1 to 2 orders of magnitude higher than that in the case where only polycrystalline silicon is used as the gate electrode material. Because it is small, it can be placed inside the gate electrode or made of the same material as the gate electrode! The signal delay within the 11 was small, which was effective for high-speed operation of the device.
第２図に示す構造においては、ソース、ドレイン領域（
２４，２５）に非常に薄い拡散層を用いても、金属配線
層（３１，３２）と接触する領域には比較的深い拡散領
域（２９，３０）を形成しであるので金属配線層（３１
，３２）がソース、ドレイン領域（２４，２５）を貫通
する仁とＫよシ発生するリークが無く、信頼性の向上が
計られる。特に、第２図−ｂ）に示すようにスルーホー
ル（２８）がソース、ドレイン１［域（２５）の端部に
！触していても、深い拡散層（３０）のために、金属配
［４（３２）とソースドレイン領域（２５）の電気的接
続はリークを生ずることなく形成できるので、装置スル
ーホールの位置ぎめに余裕ができ。In the structure shown in Figure 2, the source and drain regions (
Even if a very thin diffusion layer is used for the metal wiring layer (31, 32), a relatively deep diffusion region (29, 30) is formed in the area that contacts the metal wiring layer (31, 32).
, 32), there is no leakage that occurs when the holes and holes penetrate through the source and drain regions (24, 25), and reliability is improved. In particular, as shown in Figure 2-b), the through holes (28) are located at the ends of the source and drain regions (25)! Due to the deep diffusion layer (30), the electrical connection between the metal interconnection [4 (32) and the source/drain region (25)] can be formed without leakage, even when the device through-holes are in contact with each other. You can afford it.
ｉ！置の高密度化に効果があった。i! This was effective in increasing the density of the plant.
以上述べた様に、第２図に示す構造において社、ソース
、ドレイン領域（２４，２５）として、非常に薄い例え
ば０．３ｊｌｆｆｌの深さの拡散層を利用できるため拡
散層のゲート電極（２３）の下への回シ込みが小さく、
実効的ゲート長であるソース、ドレイン領域（２４）と
（２５）の距離の小さい、いわゆる短チヤネル型装置が
実現でき、高速動作に効果があった。よシ高速性、信頼
性を追求するには、第１図の製造方法と第２図の製造方
法を組み合わせる事が必要だが、第１図と第２図の製造
方法は単純に組みあわせる事はできない。即ち、ゲート
電極上にシリサイドを形成し九後、第２図に示す様な方
式でスルーホール部に深い拡散層を形成すると熱処理に
よシリサイド層が変質してトランジスタの閾値が変動し
た）、又酸化性の熱処理ではシリサイド層が酸化されて
、消失してしまう尋の欠点があった。特に第３図に示す
ように、半導体基体（４０）上にフィールド絶縁膜（４
１）、ゲート絶縁膜（４２）を形成した後、ゲート絶縁
膜（４３）の所要の領域に開孔部（４３）を形成し、多
結晶シリコン（４４）とシリサイド（４５）の複合構造
よりなる配線層と拡散領域（４６）の電気的接続を他の
金属配線層を介する事なく、１ｗｋ取る構造、いわゆる
埋め込みコンタクト構造を第１図に示す製造方法によシ
形成する場合には、シリサイド層（４５）の形成後の熱
処理は、シリサイド層（４５）が多結晶シリコン（４４
）の奥にまで成長し、ついには開孔部（４３）において
は、拡散領域（４６）を貫通するに至シ、拡散領域（４
６）のリーク電流を発生する為に１避けねばならない。As mentioned above, in the structure shown in FIG. 2, the gate electrode (23, ) is small.
A so-called short channel type device in which the distance between the source and drain regions (24) and (25), which is the effective gate length, is small could be realized, which was effective in high-speed operation. In order to pursue high speed and reliability, it is necessary to combine the manufacturing method shown in Figure 1 and the manufacturing method shown in Figure 2, but it is not possible to simply combine the manufacturing methods shown in Figures 1 and 2. Can not. That is, if silicide is formed on the gate electrode and then a deep diffusion layer is formed in the through-hole part using the method shown in FIG. 2, the silicide layer changes in quality due to heat treatment and the threshold value of the transistor changes.) Oxidizing heat treatment has the disadvantage that the silicide layer is oxidized and disappears. In particular, as shown in FIG.
1) After forming the gate insulating film (42), an opening (43) is formed in a required area of the gate insulating film (43), and a composite structure of polycrystalline silicon (44) and silicide (45) is formed. When forming a structure in which the electrical connection between the wiring layer and the diffusion region (46) is 1wk without going through another metal wiring layer, a so-called buried contact structure, by the manufacturing method shown in FIG. 1, silicide is used. The heat treatment after the formation of the layer (45) is performed so that the silicide layer (45) becomes polycrystalline silicon (44).
) and finally penetrate the diffusion region (46) at the opening (43).
6) must be avoided in order to generate leakage current.
本発明社以上の欠点を改善し、ゲート電極及びゲート電
極と同時に形成される配線層の材料として、多結晶シリ
コンとシリサイドの複合膜構造を有するととＫより、も
ってゲート電極及び配線層内の信号の遅れを改善し、か
つソース、ドレイン領域と金属配線層の接続部には深い
拡散層を有するために、接続部でのり−ク電振を発生す
る事なく、ソース、ドレイン領域を充分に薄くシ、もっ
て信頼性の高い、４／ｊｉチヤネル型装置を＊現する方
法を与えるものである。The present invention has improved the above drawbacks and has a composite film structure of polycrystalline silicon and silicide as the material for the gate electrode and the wiring layer formed simultaneously with the gate electrode. In order to improve signal delay and to have a deep diffusion layer at the connection between the source and drain regions and the metal wiring layer, the source and drain regions can be sufficiently connected without causing leakage vibration at the connection. It provides a method for implementing a 4/ji channel type device that is thin and highly reliable.
第４図に本発明の構成を実施例に従い説明する。The configuration of the present invention will be explained in accordance with an embodiment with reference to FIG.
半導体基体（５０）の表面に、公知の選択酸化法によシ
、厚いフィールド絶縁膜（５１）及びゲート絶縁膜（５
２）を形成し、多結晶シリコン（５３）及び窒化シリコ
ン膜（５４）の複合膜構造を有するゲート電極を形成し
、ゲート電極をマスクとして、例えばヒ素をイオン注入
する事によ）ソース、ドレイン領域（５５，５６）を形
成する。（第４図−ａ））次いで酸化性雰囲気内で熱処
理する事によハソースドレイン領域（５５，５６）の表
面に絶縁膜（５７゜５８）を形成する。同時に多結晶シ
リコン（５３）の側面には、シリコン酸化１（５９，６
ｏ）が成長するが、多結晶シリコン（５３）の表面は、
窒化シリコン膜（５４）で覆れている為に１酸化を受け
ない。（第４図−ｂ））次いで公知のフォトエツチング
法にょハ絶縁膜（５７，５８）上に第１のスルーホール
（６１，６２）を開孔し、続いて、第１のスルーホール
（６ｔ、５ｚ）ｌ’？して例えとリンを高温雰囲気中で
拡散する事によハソース、ドレイン領域（５５，５６）
よ〕深い拡散領域（６３，６４）を形成する。（第４図
−ｃ））次いで第１のスルーホール（６１，６２）Ｋｉ
ｉ続する半導体基体（５０）の表面を酸化性雰囲気内で
熱処理することによシ、絶縁膜（６５，６６）を形成し
、続いて、窒化シリコン膜（５４）を除去し無比した多
結晶シリコン（５３）の表面にシリサイド層（６７）を
形成する。（第４図−ｄ））
シリサイド層（６７）は、例えば、多結晶シリコン（５
３）の表面を算出した後に、例えば白金、タングステン
勢の金属を成長した後に、適当な熱処理を施し、然る後
に、未反応の金属をエツチング除去する事により得られ
る。続いて、表面を気相成長絶縁膜（６８）で覆う。（
第４図−６））次いで公知のフォトエツチング法で先の
第１のスルーホール（６１，６２）の位置に再び第２の
スルーホール（６９，７０）を開孔する。（第４図−ｆ
））次いで第４図−ｇ）に示す如く、例えばアルｉによ
る金属配線層（７１，７２）を形成して、ソース、ドレ
イン領域（５５，５６）からの電気的接続を深い拡散細
板（６３，６４）を介して表面に取りだして、配線する
事によシ、装置を完成する。本尖施例では明らさまに説
明しなかったが多結晶シリコン（５３）とシリサイド層
（６７）の複合膜構造の電極は、ゲート電極のみならず
配線層としても使用できることは轟然であシ、更に１第
３図に構造と同様に１ソース、ドレイン領域（５５，５
６）と同時に形成される拡散領域との電気的接続を′＃
ｌＬ接形成する、いわゆる堀め込みコンダクトを形成す
る事龜もちろん可能である。A thick field insulating film (51) and a gate insulating film (5) are formed on the surface of the semiconductor substrate (50) by a known selective oxidation method.
2), form a gate electrode having a composite film structure of polycrystalline silicon (53) and silicon nitride film (54), and use the gate electrode as a mask to ion-implant, for example, arsenic (source, drain). A region (55, 56) is formed. (FIG. 4-a)) Next, an insulating film (57.degree. 58) is formed on the surface of the hasource drain region (55, 56) by heat treatment in an oxidizing atmosphere. At the same time, silicon oxide 1 (59, 6
o) grows, but the surface of polycrystalline silicon (53) is
Since it is covered with a silicon nitride film (54), it does not undergo mono-oxidation. (Fig. 4-b)) Next, first through holes (61, 62) are opened on the insulating films (57, 58) by a known photoetching method, and then the first through holes (6t ,5z)l'? For example, by diffusing phosphorus in a high temperature atmosphere, the source and drain regions (55, 56)
deep diffusion regions (63, 64) are formed. (Fig. 4-c)) Next, the first through hole (61, 62) Ki
Insulating films (65, 66) are formed by heat-treating the surface of the semiconductor substrate (50) connected to each other in an oxidizing atmosphere, and then the silicon nitride film (54) is removed to form a unique polycrystalline film. A silicide layer (67) is formed on the surface of silicon (53). (Fig. 4-d)) The silicide layer (67) is made of polycrystalline silicon (5
After calculating the surface of 3), for example, after growing a metal such as platinum or tungsten, a suitable heat treatment is performed, and then the unreacted metal is removed by etching. Subsequently, the surface is covered with a vapor grown insulating film (68). (
(Fig. 4-6)) Next, second through holes (69, 70) are again opened at the positions of the first through holes (61, 62) using a known photoetching method. (Figure 4-f
)) Next, as shown in FIG. 4-g), metal wiring layers (71, 72) made of, for example, Al are formed, and electrical connections from the source and drain regions (55, 56) are made through deep diffusion thin plates ( 63, 64) to the surface and wiring to complete the device. Although it was not explicitly explained in the present example, it is amazing that an electrode with a composite film structure of polycrystalline silicon (53) and a silicide layer (67) can be used not only as a gate electrode but also as a wiring layer. , Furthermore, 1 source and drain regions (55, 5
6) Electrical connection with the diffusion region formed at the same time
Of course, it is also possible to form a so-called trenched conductor.
本発明によればシリサイド層（６７）の形成以後に高温
の熱処理を必要しないのでシリサイド層（６７）の異常
成長、ＭＯ８）ランジスタの閾値の変動。According to the present invention, high temperature heat treatment is not required after the formation of the silicide layer (67), so abnormal growth of the silicide layer (67) and fluctuation of the threshold value of the MO8 transistor can be avoided.
リーク電流の発生が抑制される。金属配線層（７１゜７
２）とソース、ドレイン領域（５５，５６）の接続部に
は深い拡散領域（６３，６４）が形成されているので金
属配線層（７１，７２）の半導体基体（５０）内への買
通によシリーク電流を発生する事がなく、ソース、ドレ
イン領域（５５，５６）として充分に薄い、例えば、０
．３μｍの厚さの拡散層を使用することができ、ゲート
電極の輪を狭くすることができる。The generation of leakage current is suppressed. Metal wiring layer (71°7
2) and the source/drain regions (55, 56), deep diffusion regions (63, 64) are formed, so that the metal wiring layers (71, 72) can penetrate into the semiconductor substrate (50). The source and drain regions (55, 56) are thin enough, e.g.
．． A 3 μm thick diffusion layer can be used and the gate electrode ring can be narrowed.
第４図−ｆ）に示す如く、第２のスルーホール（６９，
７０）のエツチングは、気相成長絶縁膜（６ｉ）及び絶
縁膜（６５，６６）の厚さのみを除去する事が必要なの
で％フォトレジストによるマスクが例えば第２のスルー
ホール（７０）の部分の様に絶縁膜（６６）の外１１に
私がっていても、実質的な開孔部は、第１のスルーホー
ル（６１，６２）で位置ぎめされる為に、第２のスルー
ホール（６９，７０）と深い拡散領域（６３゜６４）の
自己整合性は保たれる。更に全く同じ理由によ）、例え
第４図−Ｃ）に示すように、第１のスルーホール（６２
）がソース、ドレイン拡散領域（５６）の端部にかかつ
ていて屯、深い拡散領域（６４）が形成される為に第２
のスルーホール（７ｏ）の領域で金属配線層（７２）が
直接半導体基体（５ｏ）に接触する事は無く、リーク電
流の発生が防止される。As shown in Figure 4-f), the second through hole (69,
In the etching step 70), it is necessary to remove only the thickness of the vapor-grown insulating film (6i) and the insulating films (65, 66). Even if the hole is located outside the insulating film (66) as shown in FIG. The self-alignment of (69,70) and the deep diffusion region (63°64) is maintained. Furthermore, for exactly the same reason), as shown in Figure 4-C), the first through hole (62
) are located at the ends of the source and drain diffusion regions (56), and a deep diffusion region (64) is formed.
The metal wiring layer (72) does not come into direct contact with the semiconductor substrate (5o) in the region of the through hole (7o), thereby preventing leakage current from occurring.
以上述べた様に本発明によればゲート電極及びゲート電
極と同時に形成される配線層に、抵抗の低い多結晶シリ
コンとシリサイド層の複合膜構造を有し、かつ薄いソー
ス、ドレイン拡散層を有す石高速動作が可能で、同時に
、リーク電流閾値の変動等の少い、信頼性の高いＭＯａ
型電界効果半導体装置を得る事ができる。As described above, according to the present invention, the gate electrode and the wiring layer formed at the same time as the gate electrode have a composite film structure of low resistance polycrystalline silicon and a silicide layer, and have thin source and drain diffusion layers. A highly reliable MOa that is capable of high-speed operation and at the same time has minimal fluctuations in leakage current threshold.
type field effect semiconductor device can be obtained.
第１図（ａ）〜（ｄ）は多結晶シリ９ン及びシリティド
複合膜構造を有するＭＯ８ｇ半導体装置の従来の製造方
法を示す斜視図。第２図（膳）〜（Ｃ）ａソース。
ドレイン領域と金属配線領域との接続領域に＃！い拡散
領域を有するＭＯＢ型半導体装置の従来の製造方法を示
す断面図。第３１祉多結晶シリコン及びシリサイド複合
層構造を有する配線層と拡散領域の直接接続構造を示す
断面図。絡４ｋ（ａ＋）〜０）は本発制による製造方法
の実施例を示す断面図。
１．２０，４０・・・・・・半尋体基体、２．２１．４
１・・・・・・フィールド絶縁［，３，２２，４２，４
４・・・・・・ゲート絶縁膜、４・・・・・・ゲート電
極、５．６，２４゜２５・・・・・・ソース、ドレイン
１１１！、７．４５・・・・・・シリサイド層、８・・
・・・・絶縁膜、２７．２８・・・・・・スルーホール
、２９，３０．４６・・・・・・拡散領域、３２・・・
・・・金属配線層、４４・・団・多結晶シリコンである
◎□FIGS. 1(a) to 1(d) are perspective views showing a conventional manufacturing method of a MO8g semiconductor device having a polycrystalline silicon and silicide composite film structure. Figure 2 (Meal) - (C) a Sauce. # in the connection area between the drain area and metal wiring area! 1 is a cross-sectional view showing a conventional manufacturing method of a MOB type semiconductor device having a large diffusion region. 31 is a cross-sectional view showing a direct connection structure between a wiring layer and a diffusion region having a 31st polycrystalline silicon and silicide composite layer structure; FIG. Connections 4k(a+) to 0) are cross-sectional views showing an embodiment of the manufacturing method according to the present invention. 1.20,40...Half-fatty body substrate, 2.21.4
1...Field insulation [,3,22,42,4
4... Gate insulating film, 4... Gate electrode, 5.6, 24°25... Source, drain 111! , 7.45... Silicide layer, 8...
...Insulating film, 27.28...Through hole, 29,30.46...Diffusion region, 32...
...Metal wiring layer, 44... Group polycrystalline silicon◎□
Claims (1)
、ドレイン領域と、前記ソース、及びドレイン領域の間
の領域上にゲート絶縁膜を介して。 多結晶シリコン及び金属とシリコンの合金層から表る複
合膜構造を有するゲート電極、及び前記ゲート電極と同
一の材料よりなる配線層を備えた、ＭＯ８ｇ電界効果半
導体装置を製造するにあたヤ、前記ソース、ドレイン領
域から電気的接続を取る為のスルーホール部を介して、
前記ソース、ドレインｉ域の内部又は、前記ソース、ド
レイン領域に隣接して、前記ソース、ドレイン領域よ如
゛深い拡散領域を形成した後に、前記ゲート電極領域及
び配線層領域に無出し九多結晶シリコンの表面に金属と
シリｊンの合金層を形成する工程を有する拳會特與をす
る午尋坏鉄直の表道力汰０[Scope of Claim] Source and drain regions extending from the main surface of a semiconductor substrate and spaced apart from each other, and a region between the source and drain regions with a gate insulating film interposed therebetween. In manufacturing an MO8g field effect semiconductor device, which includes a gate electrode having a composite film structure made of polycrystalline silicon and an alloy layer of metal and silicon, and a wiring layer made of the same material as the gate electrode, Through a through-hole section for electrical connection from the source and drain regions,
After forming a deep diffusion region as deep as the source/drain region inside the source/drain i region or adjacent to the source/drain region, a non-exposed nine polycrystalline crystal is formed in the gate electrode region and wiring layer region. Omotesando Rikita 0 of Gohiro Tetsunao, who holds a special boxing tournament that involves forming an alloy layer of metal and silicon on the surface of silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4105982A JPS58158970A (en) | 1982-03-16 | 1982-03-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4105982A JPS58158970A (en) | 1982-03-16 | 1982-03-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58158970A true JPS58158970A (en) | 1983-09-21 |
Family
ID=12597840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4105982A Pending JPS58158970A (en) | 1982-03-16 | 1982-03-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58158970A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4927777A (en) * | 1989-01-24 | 1990-05-22 | Harris Corporation | Method of making a MOS transistor |
| US4935378A (en) * | 1987-03-23 | 1990-06-19 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device having more than two conductive layers |
| US4965219A (en) * | 1984-07-19 | 1990-10-23 | Sgs Microelettronica Spa | Method for the manufacturing of insulated gate field effect transistors (IGFETS) having a high response speed in high density integrated circuits |
| US5100820A (en) * | 1990-06-14 | 1992-03-31 | Oki Electric Industry Co., Ltd. | MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode |
| US5208175A (en) * | 1990-12-21 | 1993-05-04 | Samsung Electronics Co., Ltd. | Method of making a nonvolatile semiconductor memory device |
| US5612234A (en) * | 1995-10-04 | 1997-03-18 | Lg Electronics Inc. | Method for manufacturing a thin film transistor |
| US5679589A (en) * | 1989-10-17 | 1997-10-21 | Lucent Technologies Inc. | FET with gate spacer |
| US5707721A (en) * | 1995-09-29 | 1998-01-13 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors having oxidation-controlled gate lengths |
-
1982
- 1982-03-16 JP JP4105982A patent/JPS58158970A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4965219A (en) * | 1984-07-19 | 1990-10-23 | Sgs Microelettronica Spa | Method for the manufacturing of insulated gate field effect transistors (IGFETS) having a high response speed in high density integrated circuits |
| US4935378A (en) * | 1987-03-23 | 1990-06-19 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device having more than two conductive layers |
| US4927777A (en) * | 1989-01-24 | 1990-05-22 | Harris Corporation | Method of making a MOS transistor |
| US5679589A (en) * | 1989-10-17 | 1997-10-21 | Lucent Technologies Inc. | FET with gate spacer |
| US5100820A (en) * | 1990-06-14 | 1992-03-31 | Oki Electric Industry Co., Ltd. | MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode |
| US5208175A (en) * | 1990-12-21 | 1993-05-04 | Samsung Electronics Co., Ltd. | Method of making a nonvolatile semiconductor memory device |
| US5707721A (en) * | 1995-09-29 | 1998-01-13 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors having oxidation-controlled gate lengths |
| US5612234A (en) * | 1995-10-04 | 1997-03-18 | Lg Electronics Inc. | Method for manufacturing a thin film transistor |
| US5767530A (en) * | 1995-10-04 | 1998-06-16 | Lg Electronics Inc. | Thin film transistor with reduced leakage current |
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