JPS58155745A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58155745A
JPS58155745A JP58029343A JP2934383A JPS58155745A JP S58155745 A JPS58155745 A JP S58155745A JP 58029343 A JP58029343 A JP 58029343A JP 2934383 A JP2934383 A JP 2934383A JP S58155745 A JPS58155745 A JP S58155745A
Authority
JP
Japan
Prior art keywords
carrier
chip
chip carrier
pattern
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58029343A
Other languages
Japanese (ja)
Inventor
Takatsugu Takenaka
竹中　隆次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58029343A priority Critical patent/JPS58155745A/en
Publication of JPS58155745A publication Critical patent/JPS58155745A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To simplify the procedure of externally testing a chip and to shorten the wires in preparation for the stacking up of chips by a method wherein terminal pads connected to each other are provided on the upper and lower surfaces of a carrier, when a chip carrier with a semiconductor chip fixed to its rear-side recess is installed on a package substrate. CONSTITUTION:Fine ceramics or the like is formed into a chip carrier 11, and the chip carrier 11 is provided with a recess on its lower surface to house a semiconductor chip 12. The side walls and the banks on the lower surface of the carrier 11 are abutted against by a metallized pattern 16 surrounding the carrier 11. Next, the chip 12 is bonded with a conductive adhesive agent 19 to the recess in the carrier 11 and then is connected to the pattern 16 with wires 13. A process follows werein the bonding of a sealing cap 14 with an adhesive agent 15 to the lower protrusion of the pattern 16, which allows the inside of the carrier 11 to be hermetically sealed. The entirety is then mounted on a higher-order package substrate 18. Terminal pads 17 and 20 are respectively installed on the upper and lower parts of the pattern 16.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Field of application of the invention] The present invention relates to a semiconductor device.

〔従来技術〕[Prior art]

半導体装置は、半導体チップをチップキャリアに収容し
てプリント基板などの高位実装用基板に搭載して実装す
る構造をとる。A semiconductor device has a structure in which a semiconductor chip is housed in a chip carrier and mounted on a high-level mounting board such as a printed circuit board.

第１図は高位実装用基板８に搭載した従来の半導体装置
の断面図を示す。第１図において、チップキャリア１は
内面が上面に開いた空Ｐｊｒを形成するよう階段状にさ
れており、その最下部に半導体チップ２か導電性接着剤
９でダイ、ポンドされる。FIG. 1 shows a cross-sectional view of a conventional semiconductor device mounted on a high-level mounting board 8. As shown in FIG. In FIG. 1, the chip carrier 1 has a step-shaped inner surface to form an open space Pjr open to the top, and a semiconductor chip 2 is die-pounded with a conductive adhesive 9 at the bottom thereof.

チップキャリアｌには内部厳絖用メタライズドパターン
６が彫ＩＬされ、半導体チップ２と嵌続用ワイヤ３で接
続されると共に、チップキャリア１の底面に設けた外部
ｆｉｋ続用メタライズドパターン端子バクドアにｆｉ−
続される。チップキャリア１の上面には対土用キャップ
４が嵌着剤５で接着され、気密封止が行なわれる。基板
８には端子パッド７で基板８上のパターンと接続されて
搭載される。A metallized pattern 6 for internal wiring is engraved on the chip carrier l, and is connected to the semiconductor chip 2 with a fitting wire 3, and fi is connected to the metallized pattern terminal backdoor for external fik connection provided on the bottom of the chip carrier 1. −
Continued. A soil cap 4 is adhered to the top surface of the chip carrier 1 with an adhesive 5 to achieve airtight sealing. It is mounted on the board 8 and connected to the pattern on the board 8 through the terminal pad 7 .

この構造によると、半導体装置の回路機能をチェック（
テスト）する場合、特に基板に搭載された後にチ、ニッ
クする場合、１０−ブを当てるためのパターンを高位接
続用基板８に設けて行なうことが必債になる。またパタ
ーン６８−チップキャリアｌの側面に形成したものもあ
るが、側面ではプローブを当てるのに作業性が悪く、才
た機械的に行なうとする場合に当接するのが困難である
。According to this structure, the circuit function of the semiconductor device can be checked (
When testing (testing), especially when testing and nicking after mounting on a board, it is necessary to provide a pattern on the high-level connection board 8 for applying the 10-wave. There is also a pattern 68 formed on the side surface of the chip carrier 1, but it is difficult to work with the probe on the side surface, and it is difficult to contact it with a sophisticated mechanical technique.

又、従来のチップキャリアは、高位実装基板の片面もし
くは肉面に、平面的にしか実装できない為、小型化に限
界があった。Further, since conventional chip carriers can only be mounted flatly on one or the entire surface of a high-level mounting board, there is a limit to miniaturization.

〔発明の目的〕[Purpose of the invention]

本発明の目的はテスト性を高める半導体装置を提供する
ことにある。An object of the present invention is to provide a semiconductor device with improved testability.

〔発明の概豐〕[Summary of the invention]

本発明の半導体装置は、半導体チップを収容するチップ
キャリアと、半導体チップから導出され、チップキャリ
アの底面に設けられた＠ｌの端子パッドと、半導体チッ
プから導出され、チップキャリアの上面に設けられ、第
１の端子パッドと相互接続された第２の端子パッドとを
備えることを特徴とする。The semiconductor device of the present invention includes a chip carrier accommodating a semiconductor chip, a @l terminal pad led out from the semiconductor chip and provided on the bottom surface of the chip carrier, and a terminal pad led out from the semiconductor chip and provided on the top surface of the chip carrier. , comprising a first terminal pad and a second terminal pad interconnected.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の実施例を図面を参照して説明する６第２図
は本発明の一実施例を示し、高位実装用基板１８４こ搭
載した半導体装置の断面図を示す。第２図において、チ
ップキャリア１１は内面が底面に開いた空所を形成する
よう階段状にされており、内部天井面に半導体チップ１
２が導電性接着剤１９でダイボンドされる。チップキャ
リア１１はセラミックやプラスチックで構成される。チ
ップキャリア１１には内部接続用メタライズドパターン
１６が形成され、半導体チップ１２と接続用ワイヤ１３
で接続されると共に、チップキャリア１１の底面に設け
た外部接続用メタライズドパターン端子パッド１７オよ
　。Embodiments of the present invention will be described below with reference to the drawings. 6 FIG. 2 shows an embodiment of the present invention, and is a sectional view of a semiconductor device on which a high-level mounting board 184 is mounted. In FIG. 2, the chip carrier 11 has a step-shaped inner surface to form a cavity open to the bottom, and a semiconductor chip 11 is placed on the inner ceiling surface.
2 is die-bonded with a conductive adhesive 19. The chip carrier 11 is made of ceramic or plastic. A metallized pattern 16 for internal connection is formed on the chip carrier 11, and a metallized pattern 16 for internal connection is formed between the semiconductor chip 12 and the connection wire 13.
It is also connected to a metallized pattern terminal pad 17 for external connection provided on the bottom surface of the chip carrier 11.

びチップキャリア１１の上面に設けた外部接続用メタラ
イズドパターン端子パッド２０に接続される。and is connected to a metallized pattern terminal pad 20 for external connection provided on the top surface of the chip carrier 11.

底面と上面に設けられた端子バッド１７と２０は、相互
接続されることになる。封止用キャップ１４はチップキ
ャリア１１の底面から次の一つ上の段に接着剤１５で接
着され、気密封止が行なわれる。パターン１６はチップ
キャリア１１の側面に形成することができるが、端子パ
ッド１７と２０はそれぞれチップキャリア１１の底面と
上面に設けられる。基板１８には底面の端子パッド１７
で基板１８上のパターンと接続される。Terminal pads 17 and 20 provided on the bottom and top surfaces will be interconnected. The sealing cap 14 is bonded to the next level above the bottom surface of the chip carrier 11 with an adhesive 15 to achieve airtight sealing. The pattern 16 may be formed on the side surface of the chip carrier 11, while the terminal pads 17 and 20 are provided on the bottom and top surfaces of the chip carrier 11, respectively. The board 18 has terminal pads 17 on the bottom.
It is connected to the pattern on the substrate 18.

この構造によると、チップキャリア１１の上面に端子パ
ッド２０が設けられるので、これにプローブを容易に当
接することが可能となり、チェックが容易に可ｉ１シと
なる。According to this structure, since the terminal pad 20 is provided on the upper surface of the chip carrier 11, it becomes possible to easily contact the probe with the terminal pad 20, and thus it becomes easy to check.

第３図は冷却フィン２１を取り付けた場合の断面図を示
す。第３図に示すチップキャリア１１は第２図と少し形
を異するが、基本的には同一でもよい。FIG. 3 shows a cross-sectional view when the cooling fins 21 are attached. The chip carrier 11 shown in FIG. 3 has a slightly different shape from that in FIG. 2, but may be basically the same.

５１３図において、チップキャリア１１の上面に銅スタ
ッド２２を接着し、この鋼スタッド２２に冷却フィン２
１が取付けられる。この冷却フィン２１には端子バッド
２０の位置にクリアランスホール２４が設けられ、冷却
フィン２１が接触しないようにすると共に端子パッド２
０に外部からプローブ等が当接できるようにしている。In FIG. 513, a copper stud 22 is bonded to the top surface of the chip carrier 11, and a cooling fin 2 is attached to this steel stud 22.
1 is installed. This cooling fin 21 is provided with a clearance hole 24 at the position of the terminal pad 20 to prevent the cooling fin 21 from coming into contact with the terminal pad 20.
0 can be contacted by a probe or the like from the outside.

第５図は２段に積み重ねた例で、下側のチップキャリア
の端子パッド２０と上側のチップキャリアの端子パッド
１７を接続している。上側のチップキャリア１１の上面
の端子パッド２０に１０−ブ等を当接することができる
。FIG. 5 shows an example in which the chip carriers are stacked in two stages, and the terminal pads 20 of the lower chip carrier are connected to the terminal pads 17 of the upper chip carrier. A terminal pad 20 on the upper surface of the upper chip carrier 11 can be brought into contact with a terminal pad 20 or the like.

ＷＩ４図はチップキャリア１１内に複数の電気部品１２
を１ｉｌＬ、た、状態の断面図を示すもので同一符号の
ものは前記実施例と同一のものを示す。冷却フィンは第
３図の如く、銅スタッドを介して取り付けられ、この銅
スタッドは望菫しくはチップ１２対応に設けると良い。Figure WI4 shows multiple electrical components 12 inside the chip carrier 11.
This figure shows a cross-sectional view of the state shown in FIG. The cooling fins are attached via copper studs as shown in FIG. 3, and the copper studs are preferably provided corresponding to the chips 12.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、チップキャリアの上面と底面に相互接
続された端子パッドを設けているので、テスト性を鳥め
ることができる。更にメモリ素子の如き、ｔＬ　ｊｌｌ
ｊ性のある配線を多叙必要とするチップキャリアについ
ては、多段積層接続により、チツプキャ、リア間の配森
長を短縮できるので性能向上が期待できると共に、尚位
実装基板のチップキャリア実装密度を向上でき、装置の
小型化を計ることができる。According to the present invention, since the terminal pads are provided on the top and bottom surfaces of the chip carrier and are interconnected, testability can be improved. Furthermore, such as memory elements, tL jll
For chip carriers that require a large number of wiring lines, multi-stage stacked connections can shorten the wiring length between the chip carrier and the rear, which can be expected to improve performance, and also improve the chip carrier mounting density on the mounting board. This makes it possible to downsize the device.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例を示す断面図、第２図は本発明の一実施
例を示す＊ｍ図、第３図は本発明の他の実施例を示す断
面図、第４図は本発明のさらに他の実施例を示す断面図
、ｍ　ｓ図は本発明の他の実施例を示す放熱フィン付チ
ップキャリアを槓み重ねて接続した断面図である。 符号の説明 １１・・・チップキャリア　　　１２・・・半導体チッ
プ１３・・・接続用ワイヤ　　　　１４・・・封止用キ
ャップ１５・・・接層剤 １６・・・内部メタライズドパターンFig. 1 is a sectional view showing a conventional example, Fig. 2 is a *m diagram showing an embodiment of the present invention, Fig. 3 is a sectional view showing another embodiment of the present invention, and Fig. 4 is a sectional view showing an embodiment of the present invention. A sectional view showing still another embodiment, MS diagram is a sectional view showing another embodiment of the present invention in which chip carriers with heat dissipation fins are stacked and connected. Explanation of symbols 11... Chip carrier 12... Semiconductor chip 13... Connection wire 14... Sealing cap 15... Layering agent 16... Internal metallized pattern

Claims (1)

【特許請求の範囲】[Claims] 半導体チップを収容するチップキャリアと、上記半導体
チップから導出され、上記チップキャリアの底面に設け
られた＃！ｌの端子パッドと、上記チップから導出され
、上記チップキャリアの上面に設けられ、上記第１の端
子パッドと相互接続された第２の端子パッドとを備える
ことを特徴とする半導体装置。A chip carrier accommodating a semiconductor chip, and #! derived from the semiconductor chip and provided on the bottom surface of the chip carrier. 1 terminal pad; and a second terminal pad led out from the chip, provided on the upper surface of the chip carrier, and interconnected with the first terminal pad.
JP58029343A 1983-02-25 1983-02-25 Semiconductor device Pending JPS58155745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58029343A JPS58155745A (en) 1983-02-25 1983-02-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58029343A JPS58155745A (en) 1983-02-25 1983-02-25 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP5040180A Division JPS56147454A (en) 1980-04-18 1980-04-18 Packaging structure for semiconductor chip

Publications (1)

Publication Number Publication Date
JPS58155745A true JPS58155745A (en) 1983-09-16

Family

ID=12273583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58029343A Pending JPS58155745A (en) 1983-02-25 1983-02-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58155745A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065277A (en) * 1990-07-13 1991-11-12 Sun Microsystems, Inc. Three dimensional packaging arrangement for computer systems and the like

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065277A (en) * 1990-07-13 1991-11-12 Sun Microsystems, Inc. Three dimensional packaging arrangement for computer systems and the like

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