JPS58154239A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58154239A
JPS58154239A JP57038904A JP3890482A JPS58154239A JP S58154239 A JPS58154239 A JP S58154239A JP 57038904 A JP57038904 A JP 57038904A JP 3890482 A JP3890482 A JP 3890482A JP S58154239 A JPS58154239 A JP S58154239A
Authority
JP
Japan
Prior art keywords
gate
conductive layer
pipe
ceramic
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57038904A
Other languages
Japanese (ja)
Other versions
JPS6332255B2 (en
Inventor
Yuzuru Konishi
小西　讓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57038904A priority Critical patent/JPS58154239A/en
Priority to DE19833308389 priority patent/DE3308389A1/en
Publication of JPS58154239A publication Critical patent/JPS58154239A/en
Publication of JPS6332255B2 publication Critical patent/JPS6332255B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To realize application of a large capacity control current by connecting an internal control electrode ane external leadout control electrode of a semiconductor element through a conductive layer provided at the internal wall of an insulated package. CONSTITUTION:A thyristor element 2 is positioned by a guide ring 3 and a cathode copper block 7 is placed through a cathode compensating plate 6 to a ceramic metal seal 1 consisting of an anode copper block 1a, a flange 1b, a gate pipe 1c, a welding ring 1d and a ceramic cylinder 1e. The seal 1 is also provided with a stepped part 1f and a conductive layer 1g connected to the gate pipe 1c is formed at the entire part of such stepped part. The gate electrode of thyristor element 2 is connected to the conductive layer 1g with a plurality of gate lead wires 4. Since a plurality of gate lead wires 4 can be extended as explained above, a large capacity gate current can be used.

Description

【発明の詳細な説明】 この発＃ｉは半導体装置に関するものであり、特に制御
電極を有する半導体装置の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION This issue #i relates to semiconductor devices, and particularly to improvements in semiconductor devices having control electrodes.

第１図は従来のゲート・ターンオフ・サイリスクの断面
図である。このようなゲート・ターンオフ・サイリスク
は通常大電力用サイリスクと同様の平形パッケージが用
いられている。第１図において（１）　ｌｄセラミック
メタルシールであり　セラミック筒（１ｅ）に陽極鋼ブ
ロック（１ａ）とフランジαｂ）が銀ロー付され、且つ
一方の咽部には溶接リング（１ｄ）が銀ロー付されてい
る。またセラミックｖｌＪ（ｌｅ）の任意の場所にダー
トパイプ（１０）が銀ロー付されている。前記セラミッ
クメタルシール（１）にはサイリスタエレメント（２）
が設置され、ガイドリング（３）により位置決めされて
いる。サイリスクエレメント（２）には陰極補償板（６
）が載置される０サイリスタエレメント（２）のゲート
電極にアルミニューム等のゲートリード線（４）がボン
ディングされこのゲートリード線（４）にゲートスリー
ブが仲人され、この状態でセラミックメタルシール（１
）のゲートパイプ（１りに挿入される。前記陰極補償板
（６）上には電極（７）が載置されこの陰惨（７）に浴
接リング（７ａ）が取り付けられこの溶接リング（７ａ
）と溶接リング（１ｄ）が溶接される。さらにゲートパ
イプ（ＩＣ）によりセラミックシール内部空気は排気さ
れ、不活性ガスが封入されると共にゲートパイプ（ＩＣ
）の櫓部が封止溶接される。このようにしてゲートター
ンオフサイリスクは作られる。FIG. 1 is a cross-sectional view of a conventional gate turn-off sill. Such gate turn-off circuits usually use a flat package similar to high-power circuits. In Fig. 1, (1) is a ceramic metal seal, in which an anode steel block (1a) and a flange αb) are silver-brazed to a ceramic tube (1e), and a welding ring (1d) is silver-brazed to one throat. It is attached. Further, a dart pipe (10) is silver-brazed at an arbitrary location on the ceramic vlJ (le). The ceramic metal seal (1) includes a thyristor element (2).
is installed and positioned by a guide ring (3). A cathode compensation plate (6
A gate lead wire (4) made of aluminum or the like is bonded to the gate electrode of the zero thyristor element (2) on which the 0 thyristor element (2) is mounted, and a gate sleeve is attached to this gate lead wire (4). 1
) is inserted into the gate pipe (1). An electrode (7) is placed on the cathode compensation plate (6), a bath welding ring (7a) is attached to this cathode (7), and this welding ring (7a
) and the welding ring (1d) are welded. Furthermore, the air inside the ceramic seal is exhausted by the gate pipe (IC), and inert gas is filled in.
) is sealed and welded. This is how gate turn-off scissors are created.

上記従来のゲートターンオフサイリスクにおいてはゲー
ト電極とゲートリード線との接続は一般的にアルミニュ
ーム−線をボンディングすることにより行われているが
、一般のサイリスクの様なゲート電流が数アンペア根皮
のものに比ベダート・クーンオ７・サイリスタの場合は
ゲート電流が２０〜１００ム根度の大電流を取扱わなく
てはならず、このような構造では電流容量不足という間
聰があった。またゲートパイプにアルミニューム細線を
取り出して封止溶接する場合に、アルミニューム線が柔
らかく、溶接温度が低い為にアルミニューム線が断線し
たり、導電性材料である為、浴接条件が雌かしくリーク
不良が発生する場合があった０ 競 本　　は、上記従来のゲートターンオフサイリスクの欠
点を取除く為になされたものであって、絶縁容器の内壁
に設けられ外部導出側（至）電極と複い：′１ 数の金Ｉ＠細線とを互に接続する導電層を設は外部導出
制御電極に大電流を流すことができる半導体装置を提供
するものである。In the conventional gate turn-off circuit described above, the connection between the gate electrode and the gate lead wire is generally made by bonding an aluminum wire, but the gate current as in the conventional circuit is several amperes. In contrast, in the case of the Bedart Kuhn-O 7 thyristor, the gate current must handle a large current of 20 to 100 μm, and such a structure had the problem of insufficient current capacity. In addition, when taking thin aluminum wire out of the gate pipe and sealing welding it, the aluminum wire is soft and the welding temperature is low, so the aluminum wire may break, and because it is a conductive material, the bath welding conditions may be unstable. This was made to eliminate the disadvantages of the conventional gate turn-off risk described above, which sometimes caused leakage defects. Multiple:'1 The present invention provides a semiconductor device in which a large current can flow through an externally led control electrode by providing a conductive layer that interconnects a number of gold I@thin wires.

以Ｆ本実男の一実施例を第２図により詳細に説明する。Hereinafter, one embodiment of F Honjio will be explained in detail with reference to FIG. 2.

第２図にかいて％１図と同一符号は第１図に示したもの
と同等のものｔ−表わしている。１ｇ３図は第２図Ａ部
の拡大図である。（ｉ）　Ｉ／′ｉセラミックメタルシ
ールであり、セラミック筒（１り一喘に陽極鋼グロック
（ｌａ）と鉄−ニッケル系合金からなる、７ランジ（１
ｂ）が銀ロー付されている。７ランシ（１ｂ）に鉄−ニ
ッケル系合金が用いられるのはセ銀ロー付されている。In FIG. 2, the same reference numerals as those in FIG. 1 represent the same elements as those shown in FIG. Figure 1g3 is an enlarged view of section A in Figure 2. (i) I/'i ceramic metal seal with 7 flange (1 flange) made of ceramic cylinder (1 flange, 1 flange made of anode steel Glock (LA) and iron-nickel alloy)
b) is silver soldered. The iron-nickel alloy used for the 7 runci (1b) is silver soldered.

通常この材料も鉄−ニッケル系合金が用いられる。さら
にセラミックＩ＠　（１６）の壁部の任意の場所これを
貫通ずるようにケートパイプ（ＩＣ）が銀ロー付されて
いるＩ−ドパイブも通常鉄−ニッケル系合金が使われて
いる。前記ケートパイプの下部セラミック筒（１り内側
面に段部（１ｆ）が設けられており、この段部（１ｆ）
に導電層（い １ｇ）が設けられている。第３図に詳細を示すようにこ
の導電層（１ｇ）は段部（１ｆ）全面にメタライズ法で
形成すると共に、ゲートパイプ（Ｉ　Ｑ＞に接続される
。Usually, this material is also an iron-nickel alloy. Further, an iron-nickel alloy is usually used for the I-do pipe, in which a cat pipe (IC) is silver-brazed so as to pass through the wall of the ceramic I@ (16) at an arbitrary location. A step (1f) is provided on the inner surface of the lower ceramic cylinder (1) of the Kate pipe, and this step (1f)
A conductive layer (1g) is provided on. As shown in detail in FIG. 3, this conductive layer (1g) is formed on the entire surface of the step part (1f) by a metallization method, and is connected to the gate pipe (IQ>).

このような段部（１ｆ）に設けられた導電層（１ｇ）に
代え、例えば前記段部（１ｆ）を形成しないセラミック
筒（１＠）の内壁面にこれから張り出すようにダートパ
イプ（ＩＣ）にメタライズ等で接続された金Ｉ１４壌を
設けても前記導電（１ｇ）と同様の機能を達成すること
ができる。（２）はサイリスクエレメントであり、予め
、複数のｐ−ｎ接合を内部に形成した半導体クエハであ
って、一方の主面には、モリブデン等の補償板が取付け
られ、前記クエハの他方の主面Ｋｒｉそれぞれ分離形成
された、ゲートおよびカソード領域が形成され、これら
の領域にはそれぞれゲート電極、カソード電極が形成さ
れる。さらにモリブデン等よりなる陰極補償板（６）が
、前記カソード電極上に載置される。前記サイリスクエ
レメント（２）は絶縁物よりなるガイドリング（３）に
より位置決めされる。サイリスタエレメント（２）のゲ
ート電極には、アルミニューム細線等よりなる複数のゲ
ートリード線（４）が接続され、このゲートリード線（
４）は前記セラミックシール（１）内側円周面にもうけ
られた、導電層（１ｇ）に取付けられる。４電盾（１ｇ
）は十分広い面積に形成することができる為ゲート電流
の容量に応じて線径、本数を決定出来るので大電流とな
っても十分対応が出来る。ゲートリード線（４）にはゲ
ートスリーブ（５）が被覆されている。ダートスリーブ
（５）は絶縁物で作られるが絶縁チューブを用いない場
合は、絶縁塗布材料を塗布して絶縁してもよい。ゲート
リード線（４）は導電層（Ｉｇ）に半田付、ロー付、超
音波溶接等により接続　　　−される。さらにあらかじ
め溶接リング（７ａ）が取付られた陰ｆｉｍブロック（
７）を載置して前記容器リング（７ａ）と前記の溶接リ
ング（１ｄ）端部をアーク溶接より結合する。次に前記
ゲートパイプ（ＩＣ）よりセラミックシール（１）内の
空気を排気すると共に、との内部にヘリウムと磁水ガス
等よりなる不法性ガスを入れてゲートパイプ端末を封止
溶接する。Instead of the conductive layer (1g) provided on such a step (1f), for example, a dirt pipe (IC) may be formed so as to protrude from the inner wall surface of the ceramic tube (1@) that does not form the step (1f). The same function as the conductive layer (1g) can also be achieved by providing a gold I14 layer connected by metallization or the like. (2) is a silice element, which is a semiconductor quadrature in which a plurality of p-n junctions are formed in advance, and a compensating plate made of molybdenum or the like is attached to one main surface, and the other main surface of the quadrature is A gate and a cathode region are formed separately on the main surface Kri, and a gate electrode and a cathode electrode are formed in these regions, respectively. Further, a cathode compensation plate (6) made of molybdenum or the like is placed on the cathode electrode. The said risk element (2) is positioned by a guide ring (3) made of an insulator. A plurality of gate lead wires (4) made of thin aluminum wires are connected to the gate electrode of the thyristor element (2).
4) is attached to a conductive layer (1g) provided on the inner circumferential surface of the ceramic seal (1). 4 electric shield (1g
) can be formed over a sufficiently large area, so the diameter and number of wires can be determined according to the capacity of the gate current, so even large currents can be handled satisfactorily. The gate lead wire (4) is covered with a gate sleeve (5). The dart sleeve (5) is made of an insulating material, but if an insulating tube is not used, it may be insulated by applying an insulating coating material. The gate lead wire (4) is connected to the conductive layer (Ig) by soldering, brazing, ultrasonic welding, etc. Furthermore, the shade fim block (
7) is placed and the end portions of the container ring (7a) and the welding ring (1d) are joined by arc welding. Next, the air inside the ceramic seal (1) is exhausted from the gate pipe (IC), and illegal gas such as helium and magnetic water gas is introduced into the inside of the ceramic seal (1), and the end of the gate pipe is sealed and welded.

以上説明したように、大電力用トランジスタ、ゲート・
ターンオアサイリスタにおいて、ゲートリード線が何本
も取出すことが出来ることによりベース電流またはゲー
ト電流がＰ〜１００アンペア程度の大電流となっても問
題なく制御電流の大容皺化が可能となる。またペースパ
イプまたはゲートパイプに異禰金−のペースリード線ま
たはゲートリード線が挿入されない為、ペースリード線
またはゲートリード線の断線溶断等がなくなりペースオ
ープン、ゲートパイプンといった特性不良が完全になく
なる。また異種金属の溶接を行わない為ペースパイプま
たはゲートパイプ端部の封止溶接する場合にリーク不良
も完全になくなる。As explained above, high power transistors, gate
In a turn-or-thyristor, since a number of gate lead wires can be taken out, it is possible to increase the control current without any problem even if the base current or gate current becomes a large current of about P~100 amperes. In addition, since the Inekin's pace lead wire or gate lead wire is not inserted into the pace pipe or gate pipe, there is no disconnection or melting of the pace lead wire or gate lead wire, and characteristic defects such as pace open and gate pipe are completely eliminated. . Furthermore, since dissimilar metals are not welded, leakage defects are completely eliminated when sealing the ends of pace pipes or gate pipes.

以上の説明のように本発明によれば絶縁容器の内壁に設
けられ、外部導出制御電極と複数の金属細線とを互に接
続する導電層を設けたので制御電極を有する電力用半導
体装置の制御電流の大容普化がｏＴ能になるという優れ
た効果を有する。As described above, according to the present invention, a conductive layer is provided on the inner wall of an insulating container and connects an external control electrode and a plurality of thin metal wires, thereby controlling a power semiconductor device having a control electrode. It has the excellent effect of increasing the current capacity and increasing the OT capacity.

【図面の簡単な説明】[Brief explanation of the drawing]

＠　１　図ａ従来のゲート・′ターンオフ・サイリスタ
の断面図、第２図は本発明の一実施例の断面図、第３図
は第２図の要部拡大斜□視：′図である。 （１）　ｔ／ｉセラミックメタール、（１０）＃−ｔゲ
ートパイプ、　（Ｉｆ）は段部、（１ｇ）は導電層、（
２）はサイリスクエレメント、（４）Ｒゲートリード線
である。 代　理　人　　葛　　野　　　　信　　−１：。 特許庁長官殿 １．事件の表示　　　　特願昭６７−８８９０４号２、
是明の名称　　　半導体装置 ３、補正をする者 事件との関係　　　特許出願人 住　所　　　　　東京都千代田区丸の内二丁目２番３号
名　称（６０１）　　　三菱電機株式会社代表者片山仁
八部 ４、代理人 ｆＦ　所　　　　　東京都千代田区丸の内二丁目２番３
号６、補正の対象 （１）明細書の発明の詳細な説明の欄および図面の簡単
な説明の欄 （２）図面 ６、補正の内容 （１）明細書の第２頁第１行に［フランジ（（ｂ）Ｊと
あるのを［フランジ（１ｂ）Ｊと訂正する。 （２）明細書の第８頁第１１行に「溶接温度」とあるの
を「溶融温度」と訂正する。 （３）明細書の第７頁第１９行に「セラミックメタール
」とあるのを「セラミックメタルシール」と訂正する。 （４）図面の第１図および第８図を別紙のとおり訂正す
る。 ７、添付書類の目録 （１）図面（第１図、第８図）　　　　　１通Ｉｔ　　
　　　以上@1 Figure a is a sectional view of a conventional gate turn-off thyristor, Figure 2 is a sectional view of an embodiment of the present invention, and Figure 3 is an enlarged perspective view of the main part of Figure 2. (1) t/i ceramic metal, (10) #-t gate pipe, (If) is the step, (1g) is the conductive layer, (
2) is a thyrisk element, and (4) is an R gate lead wire. Agent Shin Kuzuno -1:. Mr. Commissioner of the Patent Office 1. Indication of the incident: Patent Application No. 67-88904 2,
Koreaki's name Semiconductor device 3, relationship to the amended person's case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Hitachi Katayama 4, Attorney Person fF Location: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo
No. 6, Subject of amendment (1) Column for detailed explanation of the invention and brief explanation of drawings in the specification (2) Drawing 6, Contents of amendment (1) In the first line of page 2 of the specification [ Flange ((b) J is corrected to [Flange (1b) J.) (2) On page 8, line 11 of the specification, "welding temperature" is corrected to "melting temperature." ( 3) On page 7, line 19 of the specification, "ceramic metal" is corrected to "ceramic metal seal." (4) Figures 1 and 8 of the drawings are corrected as shown in the attached sheet.7 , List of attached documents (1) Drawings (Fig. 1, Fig. 8) 1 copy It
that's all

Claims (1)

【特許請求の範囲】[Claims] 表面に内部制御電極を有する半導体素子と、この半導体
素子を囲続する絶縁容器と、この絶縁容器に設けられた
外部導出制岬電惚と、前記半導体素子の内部制御電極に
接続される複数の金ｌ１４ａ１Ｎと、前記絶縁容器の内
壁に設けられ、前記外部導出側−電極と前記複数の金属
細線とを互に接続する導電層を備えた半導体装置。A semiconductor element having an internal control electrode on its surface, an insulating container surrounding the semiconductor element, an external lead-out control cape provided in the insulating container, and a plurality of electrodes connected to the internal control electrode of the semiconductor element. A semiconductor device comprising gold l14a1N and a conductive layer provided on the inner wall of the insulating container and interconnecting the external lead-out side electrode and the plurality of thin metal wires.
JP57038904A 1982-03-09 1982-03-09 Semiconductor device Granted JPS58154239A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57038904A JPS58154239A (en) 1982-03-09 1982-03-09 Semiconductor device
DE19833308389 DE3308389A1 (en) 1982-03-09 1983-03-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57038904A JPS58154239A (en) 1982-03-09 1982-03-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS58154239A true JPS58154239A (en) 1983-09-13
JPS6332255B2 JPS6332255B2 (en) 1988-06-29

Family

ID=12538177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57038904A Granted JPS58154239A (en) 1982-03-09 1982-03-09 Semiconductor device

Country Status (2)

Country Link
JP (1) JPS58154239A (en)
DE (1) DE3308389A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110026640A (en) * 2019-05-15 2019-07-19 江阴市赛英电子股份有限公司 A kind of thin electrode ceramic soldering shell with the silver-colored structure of resistance

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0643633Y2 (en) * 1986-10-27 1994-11-14 東陶機器株式会社 Automatic bath equipment
GB2215125B (en) * 1988-02-22 1991-04-24 Mitsubishi Electric Corp Semiconductor device
JPH0781719B2 (en) * 1988-10-31 1995-09-06 リンナイ株式会社 Air conditioner heating water heater
DE19615112A1 (en) * 1996-04-17 1997-10-23 Asea Brown Boveri Power semiconductor component with two-lid housing

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1564444C3 (en) * 1966-03-24 1978-05-11 N.V. Philips' Gloeilampenfabrieken, Eindhoven (Niederlande) Semiconductor arrangement with an insulating carrier
SE373689B (en) * 1973-06-12 1975-02-10 Asea Ab SEMICONDUCTOR DEVICE CONSISTING OF A THYRISTOR WITH CONTROL POWER, WHICH SEMICONDUCTOR DISC IS INCLUDED IN A BOX
DE2534703C3 (en) * 1975-08-04 1980-03-06 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Switchable thyristor
US4236171A (en) * 1978-07-17 1980-11-25 International Rectifier Corporation High power transistor having emitter pattern with symmetric lead connection pads
DE2855493A1 (en) * 1978-12-22 1980-07-03 Bbc Brown Boveri & Cie PERFORMANCE SEMICONDUCTOR COMPONENT

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110026640A (en) * 2019-05-15 2019-07-19 江阴市赛英电子股份有限公司 A kind of thin electrode ceramic soldering shell with the silver-colored structure of resistance

Also Published As

Publication number Publication date
JPS6332255B2 (en) 1988-06-29
DE3308389A1 (en) 1983-11-17
DE3308389C2 (en) 1989-01-05

Similar Documents

Publication Publication Date Title
US4313128A (en) Compression bonded electronic device comprising a plurality of discrete semiconductor devices
US3119052A (en) Enclosures for semi-conductor electronic elements
JP2000036548A (en) Lead-through connecting assembly of double structure and its manufacture
US4835119A (en) Semiconductor device and a process of producing same
JPS58154239A (en) Semiconductor device
US4374393A (en) Light triggered thyristor device
US3950142A (en) Lead assembly for semiconductive device
GB847179A (en) Improvements in or relating to semiconductor rectifier devices
JPS5828859A (en) Leadless glass sealing diode
US3483442A (en) Electrical contact for a hard solder electrical device
JPS5855112B2 (en) Brazed structure of ceramics and Al
US3353073A (en) Magnesium-aluminum alloy contacts for semiconductor devices
JPH03177069A (en) Schottky barrier diode
JPS5855649Y2 (en) semiconductor equipment
JPH039622B2 (en)
JPS58138056A (en) Semiconductor device
JPS6233327Y2 (en)
JPH0155577B2 (en)
US3299327A (en) Housing for a three terminal semiconductor device having two insulation tube sections
US2438562A (en) Seal for electric discharge devices and method of manufacture
JPH0156526B2 (en)
JP2789484B2 (en) Semiconductor device
JPS6325739Y2 (en)
JPS60258831A (en) Microwave electron tube
JPS60178670A (en) Schottky barrier diode