JPS5815288A - Multilayer circuit board - Google Patents
Multilayer circuit boardInfo
- Publication number
- JPS5815288A JPS5815288A JP56113051A JP11305181A JPS5815288A JP S5815288 A JPS5815288 A JP S5815288A JP 56113051 A JP56113051 A JP 56113051A JP 11305181 A JP11305181 A JP 11305181A JP S5815288 A JPS5815288 A JP S5815288A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- signal wiring
- signal
- power supply
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、情報処理装置に使用される高密度配線基板に
関し、特に、信号配線層を多層につみ重ねて配線の高密
度化を容易に実現することのできる高密度多層配線基板
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-density wiring board used in an information processing device, and particularly to a high-density wiring board that can easily realize high wiring density by stacking signal wiring layers in multiple layers. It relates to a multilayer wiring board.
従来、この種の多層配線基板は、第１図に示すように、
セラミック基板ｌの表面に信号配線２および電源配線１
２を形成し、その上に気イアホール６を有する絶縁膜４
を形成して第１配線層とし、該第１配線層の上部に信号
配線８および電源配線１８を形成し、その上にグイ１ホ
ール７を有する絶縁膜５を形成して第２配縁Ｊ−とし、
該第２配−ノーの表面にグイパッド９およびＩＣ端子パ
ッド８を形成している。グイパッド９にＩＣチップ１０
を接着し、端子パッド８にリード１１を接続する構造で
ある。上述の従来の多層配線基板では、電源配線１２が
信号配？ｌ１Ａ２に比して巌暢お工び厚みが大であるこ
とから、信号配線を形成しうる面積が減少し信号配線の
高密度化が困難であるのみならず、信号配線部分と電源
配線部分の凹凸がはげしく、絶縁膜４の表面も凹凸を呈
する。このため、絶縁膜４の表面に形成し良信号配線８
の断線が生じやすいという欠点がある。配線層をさらに
多１−に設けた場合は、各配線層において上述と同様な
欠点を有する。Conventionally, this type of multilayer wiring board, as shown in FIG.
Signal wiring 2 and power wiring 1 on the surface of the ceramic substrate l
2 and has an air hole 6 thereon.
A signal wiring 8 and a power supply wiring 18 are formed on the first wiring layer, and an insulating film 5 having a hole 7 is formed thereon to form a second wiring layer. − and
A guide pad 9 and an IC terminal pad 8 are formed on the surface of the second wiring board. Guipad 9 and IC chip 10
In this structure, the lead 11 is connected to the terminal pad 8. In the conventional multilayer wiring board described above, the power supply wiring 12 is used as a signal wiring. Since the thickness of the Gannobu process is larger than that of l1A2, the area in which signal wiring can be formed is reduced, making it difficult to increase the density of signal wiring, as well as making it difficult to increase the density of signal wiring and power wiring. The surface of the insulating film 4 also exhibits unevenness. Therefore, good signal wiring 8 is formed on the surface of the insulating film 4.
The disadvantage is that wire breakage is likely to occur. If more wiring layers are provided, each wiring layer will have the same drawbacks as described above.
本発明の目的は、上述の従来の欠点を解決し、信号配線
を高密度化し、かつ、各配線層の凹凸を解消して断線の
おそれを除いた多層配線基板を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer wiring board that solves the above-mentioned conventional drawbacks, increases the density of signal wiring, eliminates unevenness in each wiring layer, and eliminates the risk of disconnection.
本発明の多層配線基板は、セラミック基板上Ｖζ、信号
配線および絶縁膜からなる配線層を多層に形成し、、＊
上部の配線層表面を、ＩＣチップを搭載する第１領域と
電源配線を形成する第２領域とに分割し、上記Ｈｚ領領
域１層以上の電源配線層を形成してなる。The multilayer wiring board of the present invention is formed by forming multiple wiring layers consisting of Vζ, signal wiring, and insulating film on a ceramic substrate, *
The upper wiring layer surface is divided into a first region where an IC chip is mounted and a second region where a power supply wiring is formed, and one or more power supply wiring layers in the Hz region are formed.
次に１本発明について、図面を参照して詳細に説明する
。Next, one embodiment of the present invention will be explained in detail with reference to the drawings.
第２図は、本発明の一実施例を示す断面図である。すな
わち、セランツク基板１上に信号配線２を形成しその上
に絶縁膜４を形成して第１信号配線層とし、該第１信号
配線層の上に信号配線８および絶縁膜５を形成して第２
信号配線層とする。FIG. 2 is a sectional view showing an embodiment of the present invention. That is, a signal wiring 2 is formed on a cellulose substrate 1, an insulating film 4 is formed thereon to form a first signal wiring layer, and a signal wiring 8 and an insulating film 5 are formed on the first signal wiring layer. Second
This is used as a signal wiring layer.
該第２信号配線層の表面を、ダイパッド９および端子パ
ッド８を形成する第１領域と、電源配線を形成する第２
領域とに分割し、上記第２領域に電源配線１４および１
６と、絶縁膜１６および１７を形成する。信号配線２．
８問および信号配線８゜端子パッド８．電源配線１４間
等はグイアホール６．７によって接続されている。The surface of the second signal wiring layer is divided into a first region where die pad 9 and terminal pad 8 are formed and a second region where power supply wiring is formed.
power supply wiring 14 and 1 in the second region.
6 and insulating films 16 and 17 are formed. Signal wiring 2.
8 questions and signal wiring 8° terminal pad 8. The power supply wirings 14 and the like are connected by guia holes 6.7.
上記信号配線２は、例えば金メツキエツチング技術によ
る周知の薄膜形成技術によって微細に形成される。信号
配線の直流抵抗は、
Ｗ；線幅 ｔ；配線の厚み
で与えられるから、例えば、配線９ｍ、配線厚さ１０ｎ
ｍの金メツキ信号−によってα５Ω７鳥の直流抵抗値を
得ることができる。このような微細配線は、厚膜印刷法
で実現することは不可能であり、上述の薄膜技術により
て形成するのが適当である。The signal wiring 2 is formed finely by a well-known thin film forming technique using, for example, gold plating etching technique. The DC resistance of the signal wiring is given by W: line width, t: wiring thickness, so for example, if the wiring is 9m and the wiring thickness is 10n.
The DC resistance value of α5Ω7 can be obtained by the gold-plated signal of m. Such fine wiring cannot be realized by thick film printing, and it is appropriate to form it by the above-mentioned thin film technology.
次に、上記絶縁膜４および６は、アルばすおよびガラス
を主成分とする無機物誘電体を印刷・焼成固化する周知
の厚膜印刷技術によって実現することができる。信号配
線２および８は、前述のように安定な金材料を用いて＊
みを小さくしているから、絶縁膜４．５の高温焼成によ
って化学的損傷を受けることはなく、かつ、絶縁膜４，
５の表面は凹凸にならず、なめらかな表面とすることが
できる。ｔた、グイアホール６および７は、絶縁ｆｉ４
＆よび５の厚膜印刷時にスクリーンによってあけられた
穴に％後工橿で厚膜金ペーストを埋め込み印刷し、絶縁
膜４および６の焼成工程で同時に焼成固化することによ
って形成することができる。すなわち、先ず信号配線２
を形成し、次に絶縁膜を印刷し、グイアフィル６を埋め
込み印刷して焼成することにより第１信号配線層が形成
される０次いで同様に第２信号配線層が形成される。Next, the above-mentioned insulating films 4 and 6 can be realized by the well-known thick film printing technique of printing and baking an inorganic dielectric material mainly composed of aluminum and glass. Signal wirings 2 and 8 are made of stable gold material as described above*
Since the diameter of the insulating film 4.5 is made small, the insulating film 4.5 is not chemically damaged by high-temperature firing, and the insulating film 4.
The surface of No. 5 is not uneven and can be made smooth. In addition, Guia holes 6 and 7 are insulated fi4
It can be formed by filling and printing a thick film gold paste into the holes made by the screen during the thick film printing of & and 5 using a post-processing machine, and simultaneously firing and solidifying the insulating films 4 and 6 in the firing process. That is, first, the signal wiring 2
A first signal wiring layer is formed by printing an insulating film, printing guiafil 6 embedded therein, and firing it. Then, a second signal wiring layer is formed in the same manner.
第２配線層の表面の前記第１領域に、ＩＣチップｌＯを
取シ付けるためのダイパッド９および端子パッド８を形
成し、第２領域に、電源配線１４゜１６および絶縁膜１
５．１６等を厚膜印刷技術によって形成する。従りて電
源配線１４．１６等は線幅および厚みを十分大とし配線
の直流抵抗を低減することが可能である。A die pad 9 and a terminal pad 8 for mounting an IC chip 1O are formed in the first region on the surface of the second wiring layer, and a power supply wiring 14° 16 and an insulating film 1 are formed in the second region.
5.16 etc. is formed by thick film printing technology. Therefore, the line width and thickness of the power supply wirings 14, 16, etc. can be made sufficiently large to reduce the direct current resistance of the wirings.
本実施例によれば電源配線１４．１６等は、第２信号配
線層の上部に形成されるから、第１および第２信号配線
層は電源配線の面積によって信号配線面積が減少するこ
とがない。すなわち、信号配線密度を向上させることが
できる効果がある。また、電源配線による凹凸は信号配
騙には何等影豐を与えないから、従来のように信号配線
が断−しやすいという欠点を解消することができる。According to this embodiment, since the power supply wirings 14, 16, etc. are formed on the upper part of the second signal wiring layer, the signal wiring area of the first and second signal wiring layers is not reduced by the area of the power supply wiring. . That is, there is an effect that the signal wiring density can be improved. Moreover, since the unevenness caused by the power wiring does not affect signal distribution in any way, it is possible to eliminate the conventional drawback that the signal wiring is easily broken.
以上のように、不発明においては、信号配線の面積を減
少させ、かつ凹凸を生じさせる電源配線を、信号配線層
の外側に形成させた構造としたから、電源配線の低イン
ピーダンス化のため、その線幅および厚みを大にしても
、信号配線領域が減少せず、かつ、信号配線は凹凸のな
い滑らかな面に形成することができる。すなわち、簡単
な構造で、容易に高密度、高信頼度の多層配線基板を実
現することができる。As described above, in the present invention, since the power supply wiring which reduces the area of the signal wiring and causes unevenness is formed outside the signal wiring layer, in order to reduce the impedance of the power supply wiring, Even if the line width and thickness are increased, the signal wiring area does not decrease, and the signal wiring can be formed on a smooth surface without unevenness. That is, it is possible to easily realize a high-density, highly reliable multilayer wiring board with a simple structure.
第１図は従来の多層配線基板の一例を示す断面図、第２
図は本発明の一実施例を示す断面図である。
図において、１・・・セラゼック基板、２，８・・・１
ぎ号配線、４，５・・・絶縁膜、６．７・・・グイアホ
ール、８・・・ＩＣ５４子パツド、９・・・ダイパッド
、１０・・・■Ｃチップ、１１・・・ＩＣリード、１４
．１６・・・颯源配置
線、１６．１７・・・絶縁膜。
代理人 弁理士住田俊宗
第１図
第２図Figure 1 is a cross-sectional view showing an example of a conventional multilayer wiring board;
The figure is a sectional view showing one embodiment of the present invention. In the figure, 1... Cerazec substrate, 2, 8... 1
No. wiring, 4, 5... Insulating film, 6.7... Guia hole, 8... IC54 child pad, 9... Die pad, 10... ■C chip, 11... IC lead, 14
．． 16... Sougen arrangement line, 16.17... Insulating film. Agent: Patent Attorney Toshimune Sumita Figure 1 Figure 2
Claims (1)
線層を多層に形成し、最上部の配線層表面を、ＩＣチッ
プを搭載する第１領域と電源配線を形成する第２領域と
に分割し、上記第２領域に１ノ一以上の電源配線層を形
成してなる多層配線基板。A multilayer wiring layer consisting of a signal wiring and an insulating film is formed on a ceramic substrate, and the surface of the uppermost wiring layer is divided into a first region where an IC chip is mounted and a second region where a power supply wiring is formed. A multilayer wiring board comprising one or more power supply wiring layers formed in the second region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113051A JPS5815288A (en) | 1981-07-21 | 1981-07-21 | Multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113051A JPS5815288A (en) | 1981-07-21 | 1981-07-21 | Multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5815288A true JPS5815288A (en) | 1983-01-28 |
Family
ID=14602246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56113051A Pending JPS5815288A (en) | 1981-07-21 | 1981-07-21 | Multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5815288A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6047496A (en) * | 1983-08-26 | 1985-03-14 | 日立化成工業株式会社 | Ceramic board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55105398A (en) * | 1979-02-08 | 1980-08-12 | Cho Lsi Gijutsu Kenkyu Kumiai | High packing density multilayer circuit board |
| JPS57100793A (en) * | 1980-12-16 | 1982-06-23 | Nippon Electric Co | High density multilayer circuit board |
-
1981
- 1981-07-21 JP JP56113051A patent/JPS5815288A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55105398A (en) * | 1979-02-08 | 1980-08-12 | Cho Lsi Gijutsu Kenkyu Kumiai | High packing density multilayer circuit board |
| JPS57100793A (en) * | 1980-12-16 | 1982-06-23 | Nippon Electric Co | High density multilayer circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6047496A (en) * | 1983-08-26 | 1985-03-14 | 日立化成工業株式会社 | Ceramic board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6366993A (en) | Multilayer interconnection board | |
| US6683260B2 (en) | Multilayer wiring board embedded with transmission line conductor | |
| JPS6352432A (en) | Semiconductor device | |
| JP3016910B2 (en) | Semiconductor module structure | |
| JPH06163794A (en) | Multilayer lead frame of metal core type | |
| JPH11233531A (en) | Structure and method for packaging electronic part | |
| JPS61131498A (en) | Wiring structure of termination circuit | |
| JPS5815288A (en) | Multilayer circuit board | |
| JPS60211897A (en) | Multilayer circuit substrate | |
| JPS6033496U (en) | Shield structure | |
| JPS59132698A (en) | Method of producing multilayer ceramic circuit board | |
| JPS5992599A (en) | Method of producing thick film hybrid integrated circuit | |
| TWI276376B (en) | Method for producing electrically conductive circuit and structure thereof | |
| JP2784209B2 (en) | Semiconductor device | |
| JPS6319896A (en) | Multilayer interconnection board | |
| JP2001053507A (en) | Wiring board and manufacturing method therefor | |
| JP2766361B2 (en) | Semiconductor device | |
| JPH0239878B2 (en) | ||
| JP2908918B2 (en) | Thick film thin film hybrid multilayer circuit board | |
| JPH0425144A (en) | Semiconductor device using tape for three-layer tab and manufacture of tape for three-layer tab | |
| JPS6149491A (en) | Ceramic multilayer circuit board | |
| JP2743524B2 (en) | Hybrid integrated circuit device | |
| JPH03110768A (en) | Chip for connecting wiring pattern | |
| JPS61292994A (en) | Manufacture of multilayer printed wiring board | |
| JP3234045B2 (en) | Multilayer wiring board |