JPS5815254A - 半導体素子の製造方法 - Google Patents

半導体素子の製造方法

Info

Publication number
JPS5815254A
JPS5815254A JP56114140A JP11414081A JPS5815254A JP S5815254 A JPS5815254 A JP S5815254A JP 56114140 A JP56114140 A JP 56114140A JP 11414081 A JP11414081 A JP 11414081A JP S5815254 A JPS5815254 A JP S5815254A
Authority
JP
Japan
Prior art keywords
layer
metal layer
solder bump
bump electrode
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56114140A
Other languages
English (en)
Inventor
Haruo Shimamoto
晴夫 島本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56114140A priority Critical patent/JPS5815254A/ja
Publication of JPS5815254A publication Critical patent/JPS5815254A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 この発明は、高密度実装基板に半導体素子を７リツプチ
ツプ方式でポンディングするために、半導体基板上に半
田バンプ電極を形成する方法の改良に関するものである
。
従来のバンプ電極構造を第１図に示す。この半導体素子
は、半導体基板（１）上にデバイス配線用の金属層（３
）を所定パターンに形成した後、金属層（３）が部分的
に露出する窓を有する絶縁保護膜（２）を形成し、次い
で金属層（３）との密着強度が良好な金属層（５）及び
半田とのぬれ性の良い金属層（６）を順次全面に蒸着し
、その後半田バンプ電極（４）を形成してこの半田バン
プ電極（４）をマスクに各金属層（５）、（６）をエツ
チングにより除去することにより作製してきた。
ところが、この従来方法によると、半田バンプ電極（４
）をエツチング液にさらす回数が多くなるため、半田バ
ンプ電極（４）を侵食する危険度が高くなりひいてはポ
ンディング強度へも影響するという欠点がある。
この発明は、上記の様な従来の方法のもつ欠点を除去す
るためになされたもので、絶縁保護膜を形成する前に配
線用金属層との密着強度の良い金属層を所定形状に形成
することにより、半田バンプ電極をエツチング液中に浸
漬する回数を減じることを目的としている。
以下、この発明の一実施例を図を用いて説明する。
第２図において、素子領域が形成された半導体基板（１
）上に、Ａ／からなる配線用の％ｌの金属層（３）と、
Ｃｒ（或いはＴｉ　、　Ｔｉ／Ｃｕ　混合層、Ｃｒ／Ｃ
ｕ混合層）からなり、第１の金属層（３）との密着強度
の良好な第２の金属層（５）を全面蒸着し、フォトレジ
ストを用いて必要な配線パターンを描き、ドライエッチ
又はクエットエッチにより第２の金属層（５）をエツチ
ングした後、この第２の金属層（５）をマスクに＠１の
金稠層（３）をエツチングし、所望の配線パターンを形
喫する。その後、絶縁法ｎ膜（２）を全面に形成し、電
極部に窓をあける。次いで、半田とのぬれ性の良い鋼か
らなる第３の金属層（６）を全面に蒸着し、フォトレジ
ストを用いて第３の金属層（６）の上ｔｉにパターニン
グを行い、メッキによって半田バンプ電極（４）を形成
する。その後、フォトレジストを除去し、第３０金鵡層
（６）を、半田バンプ電以上のようにこの発明によれば
、従来は半田バンプ電極（４）をマスクにして第２及び
第３の金属層（５）、（６）ヲエッチングをしてきたの
が、第３の金属轟けて良いことになるので、半田バンプ
電極（４）をエツチング液に浸漬する回数が減少し、半
田ノ（ンプ電極（４）の腐食を軽減することが可能とな
る。
又、第２゛の金属層のサイドエッチ量の制御が容易にで
きる。その上、アルミニツム配線上を全てクロムあるい
はチタンがおおっているため、アルミヒロックによるパ
ッシベーション膜の破壊を抑制する効果も太きい。
【図面の簡単な説明】
法 第１図は従来の製造方舅を説明するための断面図、第２
図はこの発明の一実施例を示す断面図である。 （１）・・・半導体基板、（２）・・・絶縁保鏝膜、（
３）・・第１の金属層、（４）・・・半田バンプ電極、
（５）・・・第２の金属層、（６）・・・第３の金属層
、 なお、図中同一符号は同一または相当部分を７廖す。

Claims (1)

    【特許請求の範囲】
  1. （１）半導体基板上に配線用の第１の金属層と、この第
    １の金属層との密着強度が良好な第２の金属層を所定形
    状に形成する工程、上記第１及び第２の金属層を有する
    半導体基板上に上記第２の金属層が露出する窓を有する
    絶縁膜を形成する工程、上記窓部を含んで上記絶縁膜上
    に半田とのぬれ性の良い第３の金属層を形成する工程、
    上記第３の金属層上に半田バンプ電極を形成する工程を
    含む半導体素子の製造方法。
JP56114140A 1981-07-20 1981-07-20 半導体素子の製造方法 Pending JPS5815254A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56114140A JPS5815254A (ja) 1981-07-20 1981-07-20 半導体素子の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56114140A JPS5815254A (ja) 1981-07-20 1981-07-20 半導体素子の製造方法

Publications (1)

Publication Number Publication Date
JPS5815254A true JPS5815254A (ja) 1983-01-28

Family

ID=14630137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56114140A Pending JPS5815254A (ja) 1981-07-20 1981-07-20 半導体素子の製造方法

Country Status (1)

Country Link
JP (1) JPS5815254A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172252A (ja) * 1983-03-22 1984-09-28 Hitachi Micro Comput Eng Ltd 半導体装置
JPS6357036U (ja) * 1986-09-30 1988-04-16
US5457345A (en) * 1992-05-11 1995-10-10 International Business Machines Corporation Metallization composite having nickle intermediate/interface

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS461973A (ja) * 1970-02-06 1971-10-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS461973A (ja) * 1970-02-06 1971-10-07

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172252A (ja) * 1983-03-22 1984-09-28 Hitachi Micro Comput Eng Ltd 半導体装置
JPS6357036U (ja) * 1986-09-30 1988-04-16
JPH0410990Y2 (ja) * 1986-09-30 1992-03-18
US5457345A (en) * 1992-05-11 1995-10-10 International Business Machines Corporation Metallization composite having nickle intermediate/interface
US5719070A (en) * 1992-05-11 1998-02-17 International Business Machines Corporaton Metallization composite having nickel intermediate/interface

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