JPS58148525A - Phase locked loop synthesizer - Google Patents
Phase locked loop synthesizerInfo
- Publication number
- JPS58148525A JPS58148525A JP57031149A JP3114982A JPS58148525A JP S58148525 A JPS58148525 A JP S58148525A JP 57031149 A JP57031149 A JP 57031149A JP 3114982 A JP3114982 A JP 3114982A JP S58148525 A JPS58148525 A JP S58148525A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- locked loop
- phase
- synthesizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010276 construction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は5位相同期ループ(Phase Locked
Loop以下PLLと紀す)シンセサイザ装置1%に
複数個のPLLシンセサイザ回錯を備え、該PLLシン
セサイザ回路の可変分周器の分局比t−適当に制御する
ことにより、脅威された周波数のステップ変化が相異な
る基準発振器の基*周波数の差となるように構成され7
tPLL7ン七サイザ装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention is a five-phase locked loop.
A synthesizer device 1% is equipped with a plurality of PLL synthesizer circuits, and by appropriately controlling the division ratio t of the variable frequency divider of the PLL synthesizer circuit, a step change in the threatened frequency can be realized. is the difference between the fundamental frequencies of different reference oscillators7.
This invention relates to a tPLL7 sizer device.
従来のPLLシンセサイザi&ti11は第1図に示さ
れるような構成である。すなわち、第1図において、基
準発振器1で発振された基$周波数f、は恢述する可変
分局器から出力された周波数との位相が位相検出(至)
2で比較され、位相差に対応した直流電圧が轟咳位相検
出器2から出力される。位相検出器2からの11.流旺
圧はローパスフィルタ3でその高周波成分が除去され、
低周波成分だけが抽出されてこれを電圧制御発振器4に
対する制御電圧とする。電圧制御発振器4は当該制御電
圧に対応し九出力周波数fを発生させる。電圧制御発振
64で発生した出力周波数fの信号はolJ変分周器5
の分周比N(Nは整数値)で分周され、その分局された
出力が上記位相検出02に入力される。The conventional PLL synthesizer i&ti11 has a configuration as shown in FIG. That is, in FIG. 1, the base frequency f oscillated by the reference oscillator 1 is in phase with the frequency output from the variable splitter described below.
2, and a DC voltage corresponding to the phase difference is output from the roaring phase detector 2. 11. from phase detector 2. The high frequency components of the flow pressure are removed by the low pass filter 3,
Only the low frequency component is extracted and used as the control voltage for the voltage controlled oscillator 4. The voltage controlled oscillator 4 generates nine output frequencies f in response to the control voltage. The signal of output frequency f generated by the voltage controlled oscillation 64 is sent to the olJ variable frequency divider 5.
The frequency is divided by a frequency division ratio N (N is an integer value), and the divided output is input to the phase detection 02.
このようにループが組まれ、可変分局器5の分周比Nl
変えることによって電圧制御発製器4から発生する出力
周波数fは変化する。A loop is formed in this way, and the frequency division ratio Nl of the variable divider 5 is set.
By changing this, the output frequency f generated from the voltage control generator 4 changes.
f=N @ f・ ・・・・・・・・
・(1)が成立する。f=N @ f・・・・・・・・・・
-(1) holds true.
すなわち、出力周波数ft1−変えたい場合、可変分拘
器5の分周比Nを変化させればよいが、式(1)から判
るように出力周波afは基準発振器1の基準周波数f・
の間隔、すなわちfoのステップで変化する。従がって
出力周波数fを微細に変化させようとすれば基準発振器
1の基準周波数foを低くしなければならない。基準発
振器1の基準周波数f・を低くし九場合、位相同期を安
定に保つために■−ノ臂スフィルタ3を構成する積分器
の時定数を大きくしなければならず、その結果、周波数
を切替えたとき周波数が安定するまでに時間が長くかか
り、応答が愚くなる欠点かめるため、周rBLe、のス
テップ変化のこまかいPLI、シンセサイザkrILが
作#)離かった。That is, if you want to change the output frequency ft1, you can change the frequency division ratio N of the variable divider 5, but as can be seen from equation (1), the output frequency af is the reference frequency f of the reference oscillator 1.
, that is, in steps of fo. Therefore, if the output frequency f is to be changed minutely, the reference frequency fo of the reference oscillator 1 must be lowered. When the reference frequency f of the reference oscillator 1 is lowered, it is necessary to increase the time constant of the integrator that constitutes the ■-noise filter 3 in order to maintain stable phase synchronization, and as a result, the frequency To take advantage of the disadvantage that it takes a long time for the frequency to stabilize when switching, and the response becomes poor, a PLI with fine step changes and a synthesizer krIL were created.
本@明は、上記の欠点を解決することを目的としてお夛
、複数個のPLLシンセサイザ回路を用い、該PLLシ
ンセサイザ回路の可変分局器の分局比を適当に制御し、
合成され九周波数のステップ変化が相異なる基準発振器
の基準周波数の差となるように構成することにより1周
波数のステップ変化のこまかいPLLシンセサイザ装置
ヲ提供することを目的としている。そしてそのため本発
明の位相同期ループシンセサイザ装置はり数個の位相同
期ループシンセサイザ回路であって異なる基準周波数の
信号を発振させる基準発振器と11!別に制御される可
変分局器とを備えた位相同期ループシンセサイザ回路と
、該位相同期ループシンセサイザ回路の出力周波数を混
合するミキサと、該ミキサから出力される周波数のステ
ップ変化が上記位相同期ループシンセサイザ回路のそれ
ぞれの基準発振器の基準周波数の差となるように上記可
変分局器の分周比を制御する制御器とを偏え、基準発を
器の基準周波数を低くせずに周波数のステップ変化がこ
まかくとれることを%似とじている。In order to solve the above-mentioned drawbacks, the present work uses a plurality of PLL synthesizer circuits, appropriately controls the division ratio of the variable divider of the PLL synthesizer circuit, and
It is an object of the present invention to provide a PLL synthesizer device with a fine step change of one frequency by configuring the synthesized step change of nine frequencies to be the difference between the reference frequencies of different reference oscillators. Therefore, the phase-locked loop synthesizer device of the present invention includes several phase-locked loop synthesizer circuits, including a reference oscillator that oscillates signals of different reference frequencies, and 11! a phase-locked loop synthesizer circuit comprising a separately controlled variable splitter; a mixer for mixing the output frequencies of the phase-locked loop synthesizer circuit; and a step change in the frequency output from the mixer. The controller that controls the division ratio of the variable divider is biased so that the reference frequency of each reference oscillator is different from the reference frequency of the reference oscillator, and the frequency can be changed in small steps without lowering the reference frequency of the reference oscillator. It is very similar to what you can get.
以下第2図を参照しながら説明する。This will be explained below with reference to FIG.
第2図は本発明の位相同期ループシンセサイザ装置の一
実施例tg1M構成を示している。図中、6゜7はPL
Lシy−ktイザ回路、8は建キサ、9はフィルタであ
ってミキサ8から出力された影gj!周波数を除去する
もの、10は制御器であってPLLシンセサイザ回路6
.7の各出力周波数を可変にするための制御信号を送出
するもの、11は出力端子、61は基準発振器であって
基準周波数folを発振するもの、62は位相検出器、
63はローパスフィルタ、64は電圧制御発振器、65
は可変分周器であって制御I!+10からの制御信号に
よりその分周比が変えられるもの、71は基準発振器で
あって基準周波数fog(fol @ fol )を発
振するもの、72は位相検出器、73はローパスフィル
タ、74は電圧制御発振器、75は可変分周器であって
制御器10からの制御信号によりその分周比が変えられ
るものを表わしている。FIG. 2 shows a tg1M configuration of an embodiment of the phase-locked loop synthesizer device of the present invention. In the diagram, 6°7 is PL
L-shiy-kt equalizer circuit, 8 is a mixer, 9 is a filter, and the shadow gj! which is output from the mixer 8! 10 is a controller that removes the frequency, and a PLL synthesizer circuit 6
.. 7, which sends out a control signal to make each output frequency variable; 11, an output terminal; 61, a reference oscillator that oscillates the reference frequency fol; 62, a phase detector;
63 is a low pass filter, 64 is a voltage controlled oscillator, 65
is a variable frequency divider and the control I! 71 is a reference oscillator that oscillates the reference frequency fog (fol @ fol ), 72 is a phase detector, 73 is a low-pass filter, and 74 is a voltage control device. The oscillator 75 is a variable frequency divider whose frequency division ratio can be changed by a control signal from the controller 10.
本発明のPLLシンセサイザ験置装第1図で示されるよ
うなPLLシンセサイザ回路6 、7t−2組用い、ず
キナ8によりPLLシンセサイザ回路6.7のそれぞれ
の出力周波lX11及びfat合成して周波獣fを得て
いる。The PLL synthesizer test device of the present invention uses two pairs of PLL synthesizer circuits 6 and 7t as shown in FIG. f is obtained.
今PLLシンセサイザ回路6.7のそれぞれの場合
flヨN・fil ・・・・・・・・・(2
)f、冨M IIfo、 +#H+e+
m (3)が成立する。Now, in each case of PLL synthesizer circuit 6.7, fl yo N fil ...... (2
) f, Tomi M IIfo, +#H+e+
m (3) holds true.
またPLLシンセサイザ回路6.7のそれぞれの出力鵬
波躯f!及びf、とミキサ8から出力されb周波数fと
の間には
flllllfl±f、 (蕾号任意)・・・・・・
・・・(4)の関係がある。Also, each output of the PLL synthesizer circuit 6.7 is f! and f, and the b frequency f output from the mixer 8 is fllllllfl±f (optional number)...
...There is the relationship (4).
例えばf謬f1 +f、の関係におるとき、式(2)
、 (3)を代入して
fWN・fo1+M@f、、 −・−−−・−・(
5)となる。For example, when the relationship is f error f1 + f, equation (2)
, Substitute (3) and get fWN・fo1+M@f,, −・−−−・−・(
5).
制御器lOからのflill @信号により、上記可変
分−益65の分周器Nt−1ステツプずつnステップま
で変化させ、N、N+1.N+2#・・・、N十口のよ
うに分周比全変化させると同時に、可変分周器75の分
周比Mを1ステツプずつ上記可変分周器65の分周比に
対応させて、M、M−1,M−2,・・・・・・、M−
nのように分周比が変化させられる。分局比がnステッ
プまで変化したときのZキサ8に出力される周波数fn
はfn= (N+!1 ) fo1+ (M−n )
fog −・−−−−(6)である。By the flill @ signal from the controller IO, the frequency divider of the variable gain 65 is changed by Nt-1 steps up to n steps, N, N+1 . At the same time, the frequency division ratio M of the variable frequency divider 75 is made to correspond to the frequency division ratio of the variable frequency divider 65 one step at a time, so that M, M-1, M-2,..., M-
The frequency division ratio is changed as n. Frequency fn output to Z mixer 8 when the division ratio changes up to n steps
is fn= (N+!1) fo1+ (M-n)
fog ------(6).
制御器10からの制御信号により、可変分周器as、7
sの分周比を1xテツプずつnステップまで変化させ九
ときの建キサ8に出力される周波数の変化幅Δfnは式
(5) 、 (6)からJfnxxfn−f=n (f
oe−fog ) =−−・・−(7)となり、1x
テツプm9のミキt8に出力される周波数の変化幅jf
はPI、Lシンセサイザ回路6の基準側gi ljL
f o 1とPLLシンセサイザ回路7の基準周波数f
o3との差で決まり、各基準発振器61゜71の基準周
波ML fott fogよシ低い周波数が得られる。According to the control signal from the controller 10, the variable frequency divider as, 7
When the frequency dividing ratio of s is changed by 1x steps up to n steps, the change width Δfn of the frequency output to the building mixer 8 is calculated from equations (5) and (6) as follows: Jfnxxfn-f=n (f
oe−fog ) =−−・・−(7), and 1x
Frequency change width jf output to mixer t8 of step m9
is the reference side gi ljL of the PI, L synthesizer circuit 6
f o 1 and the reference frequency f of the PLL synthesizer circuit 7
o3, and a frequency lower than the reference frequency ML fott fog of each reference oscillator 61, 71 can be obtained.
すなわち、各基準発振器61,71の基準周波数foe
、 fogより低いJi11波数間隔(ステップ)で建
キナ8に出力される周波数ft変化させることができる
。That is, the reference frequency foe of each reference oscillator 61, 71
, it is possible to change the frequency ft output to the construction sensor 8 at Ji11 wave number intervals (steps) lower than fog.
同様に式(4)において、例えばf=fl −f、の関
係の場合は、制御器lOからの制御信号により、可変分
局器65.75の分周比はN、N+1.N+2゜・・・
・・・、Nulmのように変化させられるのに対し、M
。Similarly, in equation (4), for example, in the case of the relationship f=fl - f, the frequency division ratio of the variable divider 65.75 is N, N+1, . N+2°...
..., while it can be changed like Nulm, M
.
Mal、M+2.・・・・・・、Mhoの如く変化させ
られる。Mal, M+2.・・・・・・It can be changed like Mho.
nステップまで変化させたときのンキサ8に出力される
周波数の変化幅Δfnは式(7)のようになり、上記説
明の様に同一結果が得られる。式(4)の他の関係につ
いても全く同様である。The width of change Δfn of the frequency output to the encoder 8 when the frequency is changed up to n steps is expressed by equation (7), and the same result as described above can be obtained. The same holds true for the other relationships in equation (4).
このようにPLLシンセサイザ回路6の基準周波数fo
1及びPLLシンセサイザ回路7の基準周波数fO1と
その可変分局器65.75の分局比の変化の方向を適尚
に設定しておけば、基準発振器61.71の各基準周t
IjL数fol、 fogよシ低い周波数のステップ変
化が可能なPLLシンセサイザ装置ができることになる
。In this way, the reference frequency fo of the PLL synthesizer circuit 6
1 and the direction of change in the reference frequency fO1 of the PLL synthesizer circuit 7 and the division ratio of the variable division divider 65.75, each reference frequency t of the reference oscillator 61.71 can be set appropriately.
A PLL synthesizer device capable of step change in frequencies lower than the IjL numbers fol and fog can be created.
2キサ8から出力された周波数fQD信号はフィルタ8
に入力され、当該ミキサ8で発生した影導周改数の信号
がフィルタ8で除去されて目的とする周波数fの信号が
出力端子11に出力される。The frequency fQD signal output from the 2 xer 8 is passed through the filter 8.
The signal of the shadow frequency change generated by the mixer 8 is removed by the filter 8, and a signal of the target frequency f is outputted to the output terminal 11.
以上説明した如く、本発明によれば、複数個のPLLシ
ンセサイザ回路を制御しそれぞれの出力周波数を合成し
て目的の周波数を得るようにしているので、PLLシン
セサイザ回路の基準周波数が鳥い基準発振器を用いて周
波数のステップ変化の小さいPLLシンセサイザ装置を
容易に作ることができる。そして周波数を微細に変化さ
せる場合でもPLLシンセサイザ回路の基準発振器の基
準周波数は高いので、ローノ臂スフィルタを構成する積
分器の時定数が小さくでき1周波数の切替に要する時間
が短縮される。As explained above, according to the present invention, a plurality of PLL synthesizer circuits are controlled and their respective output frequencies are synthesized to obtain a target frequency. Using this, a PLL synthesizer device with small step changes in frequency can be easily created. Even when changing the frequency minutely, the reference frequency of the reference oscillator of the PLL synthesizer circuit is high, so the time constant of the integrator constituting the Ronos filter can be made small, and the time required to switch one frequency can be shortened.
第1図は従来の位相同期ループシンセサイザ装置の回路
構成、第2図は本発明の位相同期ループシンセサイザ装
置の一実施例回路構成を示している。
凶中、lFi基準発畿器、2は位相検出器% 3はロー
ノ々スフィルタ、4は電圧制御発振器、5は可変分周器
、6.7dPLLシンセサイザ回路、8は2キサ、9は
フィルタ、10は制御器、61゜71は基準発振器、6
5.75は、可変分周器を表わしている。
特許出願人 安立電気株式会社FIG. 1 shows the circuit configuration of a conventional phase-locked loop synthesizer device, and FIG. 2 shows the circuit configuration of an embodiment of the phase-locked loop synthesizer device of the present invention. In the middle, lFi reference oscillator, 2 is phase detector%, 3 is low-noise filter, 4 is voltage controlled oscillator, 5 is variable frequency divider, 6.7dPLL synthesizer circuit, 8 is 2x, 9 is filter, 10 is a controller, 61° 71 is a reference oscillator, 6
5.75 represents a variable frequency divider. Patent applicant Anritsu Electric Co., Ltd.
Claims (1)
る基準周波数を発振させる島準発振器と個別に制御され
る可変分周器とを備えた位相同期ループシンセサイザ回
路と;該位相同期ループシンセサイザ回路の出力周波数
を混合するミキサと;該ミキサから出力される周波数の
ステップ変化が上記位相同期ループシンセサイザ回路の
それぞれの基準発振器の基準周波数の差となるように上
記可変分周器の分周比を制御する制御器とを備えてなる
位相園期ルーズシンセサイザ装置。A phase-locked loop synthesizer circuit comprising a plurality of phase-locked loop synthesizer circuits, the circuit having island quasi oscillators that oscillate different reference frequencies and individually controlled variable frequency dividers; an output frequency of the phase-locked loop synthesizer circuit; a mixer for mixing; and control for controlling the division ratio of the variable frequency divider so that a step change in the frequency output from the mixer becomes a difference between the reference frequencies of the respective reference oscillators of the phase-locked loop synthesizer circuit. A phase-based loose synthesizer device that is equipped with a device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57031149A JPS58148525A (en) | 1982-02-28 | 1982-02-28 | Phase locked loop synthesizer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57031149A JPS58148525A (en) | 1982-02-28 | 1982-02-28 | Phase locked loop synthesizer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58148525A true JPS58148525A (en) | 1983-09-03 |
Family
ID=12323375
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57031149A Pending JPS58148525A (en) | 1982-02-28 | 1982-02-28 | Phase locked loop synthesizer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58148525A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61216529A (en) * | 1985-03-22 | 1986-09-26 | Kokusai Electric Co Ltd | Inductive radio frequency synthesizer device |
JPH02166904A (en) * | 1988-12-21 | 1990-06-27 | Nec Corp | Compound frequency synthesizer |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5338956A (en) * | 1976-09-21 | 1978-04-10 | Matsushita Electric Ind Co Ltd | Frequency generator circuit |
JPS5398766A (en) * | 1977-02-08 | 1978-08-29 | Marukon Denshi Kk | Pll synthesizer |
-
1982
- 1982-02-28 JP JP57031149A patent/JPS58148525A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5338956A (en) * | 1976-09-21 | 1978-04-10 | Matsushita Electric Ind Co Ltd | Frequency generator circuit |
JPS5398766A (en) * | 1977-02-08 | 1978-08-29 | Marukon Denshi Kk | Pll synthesizer |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61216529A (en) * | 1985-03-22 | 1986-09-26 | Kokusai Electric Co Ltd | Inductive radio frequency synthesizer device |
JPH02166904A (en) * | 1988-12-21 | 1990-06-27 | Nec Corp | Compound frequency synthesizer |
JPH0612854B2 (en) * | 1988-12-21 | 1994-02-16 | 日本電気株式会社 | Frequency synthesizer |
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