JPS5814567A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS5814567A JPS5814567A JP56111953A JP11195381A JPS5814567A JP S5814567 A JPS5814567 A JP S5814567A JP 56111953 A JP56111953 A JP 56111953A JP 11195381 A JP11195381 A JP 11195381A JP S5814567 A JPS5814567 A JP S5814567A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- conductors
- polycrystalline
- film
- fusing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明社半導体装置及びその製造方法に係わシ、特に必
１！に応じて、開いていた回路間を結線し、更に又その
後、該回路間を開くこともで龜る技術に関する。[Detailed Description of the Invention] Regarding the present invention's semiconductor device and its manufacturing method, especially the following are essential! The present invention relates to a technique that makes it difficult to connect open circuits in accordance with the situation, and then to open the circuits.
従来、例えば、一度メモリに書き込んでしまえば二度と
変更する必要の無い情報とか、使用頻度が多い情報など
はその情報だけを固定し、読み出し専用化した方が便利
な場合かあ〉、読み出し専用メモリ（ＲＯＭ ： Ｒｅ
ａｄ ０ｎｌｙ Ｍｅｍｏｒｙ）とシテ用いられている
。このような読み出し専用メモリを作る時は、通常、ヒ
凰−〆を過電流で溶断し、このヒ為−ズの有無で情報を
書き込む方法や、ダイオ−ドラトリクスを構成し、その
ダイオードを過電圧で破壊して情報を書き込む方法等が
とられ、いずれも従来閉回路でＴｏ−）た所を開いて情
報を書き込んでいる。Conventionally, for example, for information that does not need to be changed once it is written to memory, or information that is frequently used, it may be more convenient to fix only that information and make it read-only. (ROM: Re
ad 0nly Memory). When making such a read-only memory, there is usually a method in which the heat shield is fused with an overcurrent and information is written in the presence or absence of this heat, or a diode matrix is constructed and the diode is fused with an overvoltage. Methods such as destroying the circuit and writing information on it are used, and in both cases, information is written by opening the circuit that was previously a closed circuit.
更に又、例えば、−密度に集積化されたランダム・アク
セス・メモリ（ＲＡＭ）の場合、少数ビットの不良を救
うため、予め予備のメモリ回ｗ６ｔ−用意しておき、当
初のメモリ回路に不良ビット箇所が生じた時、該予備の
回路全使用する方法もある。Furthermore, for example, in the case of densely integrated random access memory (RAM), a spare memory circuit is prepared in advance to save a small number of defective bits, and the defective bits are added to the original memory circuit. There is also a method of using all of the spare circuits when a problem arises.
この場合はその必要性が生じた時のみ予備回路を結合す
れば、よいのであるが、従来適切な方＠が無かりたため
、初めからその予備回路を結縁しておき、先のヒ為−ズ
あるいはダイオードを溶断、破壊する方法で必要回路を
得ていた。そのため、元々本体が良品であっても予備回
路を切り離す作業が必要であった。In this case, it would be a good idea to connect the backup circuit only when the need arises, but since there was no suitable way to do so, it is best to connect the backup circuit from the beginning to prevent future damage. Alternatively, the necessary circuit was obtained by blowing out and destroying the diode. Therefore, even if the main unit was originally a good product, it was necessary to disconnect the spare circuit.
本発明の目的は、溶断、破壊するのみでなく、必要に応
じ回路全結線する技術を提供することにある。An object of the present invention is to provide a technique that not only fuses and destroys the circuit, but also connects the entire circuit as necessary.
本発明は互いに離間している導電通路間を不純！＃！Ｊ
ｔ−含有する単結晶シリコン又は多結晶シリコン材料に
よ〉結縁されている構造を有す半導体装置である。The present invention eliminates impurities between conductive paths that are spaced apart from each other. #! J
This is a semiconductor device having a structure in which the semiconductor device is bonded by a t-containing single crystal silicon or polycrystalline silicon material.
更に又、本発明は互いに離間している導電通路間に、該
導電通路を構成している両材料の端に載るように、低温
で成長させた不純物を多く含みながら４高抵抗の多結晶
シリコンか、又は低温で成長させた多結晶クリコンにイ
オン注入を行りて高抵抗とした多結晶シリコンを配置す
る工程と、該高抵抗の多結晶シリコンにレーザー元又は
電子ビームを照射して低抵抗化せしめ、該離間していた
導電通路間管電気的に結縁する工程とｔ含むことｔ％徴
とする半導体装置の製造方法で多る。Furthermore, the present invention provides a method for applying polycrystalline silicon having high resistance and containing a large amount of impurities, which is grown at a low temperature, between the conductive paths which are spaced apart from each other, so as to be placed on the ends of both materials constituting the conductive paths. Alternatively, there is a process of placing polycrystalline silicon with high resistance by implanting ions into polycrystalline silicon grown at low temperature, and irradiating the high resistance polycrystalline silicon with a laser source or an electron beam to make the resistance low. There are many methods for manufacturing semiconductor devices which include a step of electrically connecting the separated conductive paths.
本発明により単に溶断により回路奮闘くのみでなく、導
通によ）回路全閉じる事もできるようにな）、回路設計
の自由度と、プロセス設計の自由［１−著しく増すこと
ができる。According to the present invention, it is now possible not only to close the circuit by simply blowing the circuit, but also to completely close the circuit by conducting the circuit.The degree of freedom in circuit design and process design can be significantly increased.
次に本発明の実施例を図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
第１図四〜（ト）は本発明の典型的な実施例の工程を示
す断面図である。即ち、先ず、例えば通常のウェハ拡散
工程管終えた、二酸化シリコンの如き絶縁保護膜１０１
ｔ−有す、Ｐ型γリコン基板１０２上に、一つの回路
の配線導体１０３と別の回路の配縁導体１０４とｔＸＸ
第１囚囚ように配置させる。この配置導体１０３，１０
４は通常側われているアルミニウムや多結晶シリコ／で
も、あるいはモリブデンの如き高融点金属でも、あるい
は又、金属硅化物でもよい。次いで、第１図の）のよう
にその上に絶縁保護膜１０５ｔ−付層させる。絶縁保護
膜１０５としては例えば、リンを少量含む二酸化シリコ
ンを用いるとよい。次に第１図（Ｑの如く、通常のホト
レジスジ法により、前記一つの回路の配線導体１０３４
別の回路の配縁導体１０４の端部を露出させるように、
絶縁保＠ｇｔｏｓｔ−選択エッチイグする。次いで第１
図００ように、完配一つの口締の配線導体１０３の端部
と別の回路の配線導体１０４の端部とを覆うように高抵
抗の多結晶シリデン１０６ ｅ付着する。このような高
抵抗、の多結晶シリコン１０６は例えば、シラン！？Ｏ
ＯＣ８度の比較的低温で熱分解して、約３００１＾〜５
ｏｏｏλの厚さに成長し、次いで例えば、Ｕｐ＋イ＃
ｙ １ ｓ ｏ ｋｅＶカラ２００ ｋｅＶ迄Ｏ間Ｏエ
ネルギー範囲を変化させなからｌ Ｑ ’／ 偉程度イ
オン注入ｔ−施すとと≦よシ、２０〜１．ｏ ｏ ＨΩ
の膜が得ら些るので、それ金利用して形成できる。FIGS. 4-4(g) are cross-sectional views showing the steps of a typical embodiment of the present invention. That is, first, an insulating protective film 101, such as silicon dioxide, is formed after a normal wafer diffusion process.
A wiring conductor 103 of one circuit, a wiring conductor 104 of another circuit, and a tXX
Place them like the first prisoner. This arranged conductor 103, 10
4 may be aluminum or polycrystalline silicon, which is commonly used, or a high melting point metal such as molybdenum, or a metal silicide. Then, as shown in FIG. 1), an insulating protective film 105t is formed thereon. As the insulating protective film 105, for example, silicon dioxide containing a small amount of phosphorus may be used. Next, as shown in FIG. 1 (Q), the wiring conductor 1034 of the one circuit is
so as to expose the ends of the wiring conductors 104 of another circuit.
Insulation @gtost - Selective etch. Then the first
As shown in FIG. 00, high-resistance polycrystalline silidene 106e is deposited to cover the end of the wiring conductor 103 of one circuit and the end of the wiring conductor 104 of another circuit. Such a high-resistance polycrystalline silicon 106 is made of, for example, silane! ? O
It is thermally decomposed at a relatively low temperature of 8 degrees OC to about 3001^~5
grown to a thickness of oooλ and then, for example, Up+I#
y 1 s o keV to 200 keV without changing the O energy range between 0 and 200 keV, 20 to 1. o o HΩ
The film can be formed by using gold.
この段階迄は完配一つの回路の配線導体１０３と別の回
路の配線導体１０４ とｔｉ回路的には結合されていな
い。しかし、このよ裏に不純物を充分含みながら、イオ
ン注入時のイオンビーム照射損傷による高抵抗は、例え
ばＫｒ＋ レーザーを用い７９−レンズで６ワツトーの
レーザー元を照射することにより７０〜１００Ωという
低抵抗の多結晶シリコン１０７に転じ、ＷｆＪ１図（至
）のように１．完配一つの回路の配縁導体１０３、と、
別の回路の配線導体１０４とを電気回路的に閉回路する
ことができる。Up to this stage, the wiring conductor 103 of one circuit is not connected to the wiring conductor 104 of another circuit in a ti-circuit manner. However, the high resistance caused by ion beam irradiation damage during ion implantation can be reduced to 70-100Ω by irradiating a 6W laser source with a 79-lens using, for example, a Kr+ laser. 1. As shown in Figure WfJ1 (to), the polycrystalline silicon 107 of A wiring conductor 103 of one complete circuit, and
It is possible to form a closed electrical circuit with the wiring conductor 104 of another circuit.
第２図囚〜（ｑは一度閉回路にしたものを再度開口Ｗ＆
にする技術の実施例上順次説明する断面図で多る。即ち
、前例同様、例えば二酸化シリコンの） 如き、絶縁
保ｌＩ膜２０１を被覆した拡散工程の終了したシリコン
基板２０２ｔ−用意する。但しζこで線、その絶縁保護
膜２０１上に一つの回路の配縁導体２０３と別の回路の
配縁導体２０４とを構成し、絶縁保護膜２０５で被覆し
て端部のみホト、 Ｖシスト法で露出して、高抵抗
の多結晶シリコン２０６で両配蔽導体の端部を覆うよう
に、＠２図（４）の如く構成する時、その高抵抗多結晶
シリコン２０６の下に、リン拡散部２０７ ’？配装し
ている点が一つの特徴である。この第２図（１）で社、
まだ両回路間は開いている。Figure 2 ~ (q is once a closed circuit that is opened again W &
There are many cross-sectional views that will be sequentially explained as examples of the technology. That is, as in the previous example, a silicon substrate 202t coated with an insulating lI film 201, such as silicon dioxide (for example), which has undergone a diffusion process, is prepared. However, the wiring conductor 203 of one circuit and the wiring conductor 204 of another circuit are formed on the insulating protective film 201 of the wire, and it is covered with an insulating protective film 205 and only the ends are photo-photographed. When configuring the structure as shown in Figure 2 (4) to cover the ends of both wiring conductors with high-resistance polycrystalline silicon 206 exposed by the method, phosphorus is placed under the high-resistance polycrystalline silicon 206. Diffusion section 207'? One of its features is the way it is arranged. In this figure 2 (1),
Both circuits are still open.
次に前例の如くイオン注入法とレーザー又は電子ビーム
アニール法にょシ、この高抵抗の多結晶シリコン２０６
ｔ−、！２図（５）のように、低抵抗の多結晶シリコ
ン２０８に変換する。この段階で完配一つの回路の配線
導体２０３ と、別の回路の配線導体２０４とが結合
されたことになる。アニールの条件及び低抵抗の多結晶
シリコン２０８のパターン形状によシ、この多結晶シリ
コン２０８は従来ＯＦ−ａ−−スとしても使用できる。Next, as in the previous example, ion implantation and laser or electron beam annealing were performed to form this high-resistance polycrystalline silicon 206.
T-,! As shown in FIG. 2 (5), it is converted to low resistance polycrystalline silicon 208. At this stage, the wiring conductor 203 of one circuit and the wiring conductor 204 of another circuit are completely connected. Depending on the annealing conditions and the pattern shape of the low-resistance polycrystalline silicon 208, this polycrystalline silicon 208 can also be used as a conventional OF-a-base.
そのヒユーズとして用いた場合、溶断した例が第２図０
である。When used as a fuse, an example of a blown fuse is shown in Figure 2.
It is.
溶断箇所２０９で絶縁保護膜２０１が露出するので、こ
こに予め、リン拡散部２０７が設けられてオシ、不純物
イオンの汚染を阻止している。この！１１！施例で紘、
閉回路から開回路へ転換できるので、書き換え可能な読
出し専用メモリとして活用できる。Since the insulating protective film 201 is exposed at the melting point 209, a phosphorus diffusion portion 207 is provided here in advance to prevent contamination by impurity ions. this! 11! Hiro in the example,
Since it can be converted from a closed circuit to an open circuit, it can be used as a rewritable read-only memory.
上述の実施例では、いずれも配朦導体材料間を結合する
例を述べたが、この配線導体は拡散層を用いても良いこ
とは云う迄もない。In the above-mentioned embodiments, examples have been described in which wiring conductor materials are coupled, but it goes without saying that a diffusion layer may be used as the wiring conductor.
即ち、＠３図のようにＰ型シリコン基板３０１にｎ型拡
散層３０２が配線導体として用いられてお〕、絶縁保護
膜３０３ｔ−介して別の回路への配線導体３０４が形成
されている時にも、前例同様、低抵抗の多結晶シリコン
３０５會イオン注入法とレーザーアニール法との結合に
よ）構成できる。That is, when an n-type diffusion layer 302 is used as a wiring conductor in a P-type silicon substrate 301 as shown in Figure 3, and a wiring conductor 304 to another circuit is formed through an insulating protective film 303t. Similarly to the previous example, this can be constructed by combining low-resistance polycrystalline silicon 305 ion implantation and laser annealing.
本発明によシ、先ず第１に、従来、閉回路であったもの
を開にして情報を入れていたシ、あるいは予備回路を使
用していたが、本発明を用いると予備回路は初めから開
いておけるので、予備回路が必要になった時点で閉じれ
ばよい。According to the present invention, first of all, in the past, a closed circuit was opened to input information, or a backup circuit was used, but with the present invention, the backup circuit is established from the beginning. Since it can be left open, it can be closed when a backup circuit is needed.
また、本発明の第２の効果として、一度閉じて用いても
、不要になりた時、ヒ為−ズ溶断万式で再び開けること
ができるという利点が生ずることをあげることができる
。A second advantage of the present invention is that even if the device is closed and used, it can be opened again when it is no longer needed.
同、本発明は実施例として、シリコン半導体の例を用い
たが、他の半導体デバイスでもよいことは云う迄もない
。又、高抵抗から低抵抗へ転じ、かつヒユーズとしても
用いられる材料として多結晶シリコンを例にとったが、
これは多結晶の他の半導体でもよく、又、レーザーアニ
ールなどにより、必ずしも多結晶でなく単結晶に転じる
場合もある。Similarly, although the present invention uses a silicon semiconductor as an example, it goes without saying that other semiconductor devices may be used. In addition, we took polycrystalline silicon as an example of a material that can be used as a fuse, changing from high resistance to low resistance.
This may be another polycrystalline semiconductor, or may be converted into a single crystal rather than a polycrystal by laser annealing or the like.
第４図（５）から（Ｅ）迄は、本発明の典型的な実施例
の工程を示す断面図でｔりシ、第２図（５）から０迄は
本発明の第２の実施例の工程を順次説明する断面図であ
〉、更に第３図は本発明の他の実施例を示す断面図であ
る。
主な記号
１０１．１０５，２０１，２０５，３０３−・・・・・
絶縁保護膜、１０２，２０２．３０に−・・・Ｐ型シリ
コン基板、１０３．２０３・・・・・・一つの回路の配
線導体、１０４゜２０４．３０４・・・・・・別の回路
の配縁導体、１０６゜２０６．３０５・・・・・・高抵
抗の多結晶シリコン、１０７゜２０８・・・・・・低抵
抗の多結晶シリコン、２０７・・・・・・リン拡散部、
２０９・・・・・・溶断個所、３０２・・・・・・ｎ型
拡散層。
ブ、゛・ｆ−心。
代理人 弁４士 内 原 晋し、；、）峯 Ｉ
Ｔ￥］
２．ｔｔ
￥＝２回FIG. 4 (5) to (E) are cross-sectional views showing the steps of a typical embodiment of the present invention, and FIG. 2 (5) to 0 are cross-sectional views of a second embodiment of the present invention. FIG. 3 is a sectional view sequentially explaining the steps of FIG. 3, and FIG. 3 is a sectional view showing another embodiment of the present invention. Main symbols 101.105, 201, 205, 303-...
Insulating protective film, 102, 202.30 - P-type silicon substrate, 103.203... Wiring conductor of one circuit, 104° 204.304... Wiring conductor of another circuit Wiring conductor, 106°206.305... High resistance polycrystalline silicon, 107°208... Low resistance polycrystalline silicon, 207... Phosphorus diffusion part,
209...Fusion point, 302...N-type diffusion layer. B, ゛・f-heart. Agent: Susumu Uchihara, 4 Benshi, ;,) Mine I
T￥] 2. tt ¥=2 times
Claims (2)
ｉる導電通路間を不純物を含有する単結晶シリコン又は
多結晶シリコン材料で結線した構造を有す半導体装置。(1) A semiconductor device having a structure in which conductive paths spaced apart from each other in a conductive portion of the semiconductor device are connected with a single crystal silicon or polycrystalline silicon material containing impurities.
、互いに離間してｉる導電通路間に、誼導電通路を構成
している両材料の端部を覆うよう、不純物を含みながら
も高抵抗の多結晶シリコンで結崖し、次いで必要な個所
のみレーザー党、ある転換する工程金倉むことｔＩｆ＃
徴とする半導体装置の製造方法。(2) Semiconductor f! In the process of forming a conductive part, a high-resistance polycrystalline material containing impurities is placed between the conductive paths separated from each other so as to cover the ends of both materials constituting the conductive path. Silicon is applied, and then only the necessary areas are laser-converted, which is a conversion process.If #
A method for manufacturing a semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111953A JPS5814567A (en) | 1981-07-17 | 1981-07-17 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111953A JPS5814567A (en) | 1981-07-17 | 1981-07-17 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5814567A true JPS5814567A (en) | 1983-01-27 |
Family
ID=14574290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56111953A Pending JPS5814567A (en) | 1981-07-17 | 1981-07-17 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5814567A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61229346A (en) * | 1985-02-23 | 1986-10-13 | エステイ−シ− ピ−エルシ− | Formation of polychrystal silicon on integrated circuit |
| WO1992007380A1 (en) * | 1990-10-15 | 1992-04-30 | Seiko Epson Corporation | Semiconductor device having switching circuit to be switched by light and its fabrication process |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4933231A (en) * | 1972-07-27 | 1974-03-27 |
-
1981
- 1981-07-17 JP JP56111953A patent/JPS5814567A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4933231A (en) * | 1972-07-27 | 1974-03-27 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61229346A (en) * | 1985-02-23 | 1986-10-13 | エステイ−シ− ピ−エルシ− | Formation of polychrystal silicon on integrated circuit |
| WO1992007380A1 (en) * | 1990-10-15 | 1992-04-30 | Seiko Epson Corporation | Semiconductor device having switching circuit to be switched by light and its fabrication process |
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