JPS58142627A - Gate circuit of self arc extinction type semiconductor element - Google Patents
Gate circuit of self arc extinction type semiconductor elementInfo
- Publication number
- JPS58142627A JPS58142627A JP57023553A JP2355382A JPS58142627A JP S58142627 A JPS58142627 A JP S58142627A JP 57023553 A JP57023553 A JP 57023553A JP 2355382 A JP2355382 A JP 2355382A JP S58142627 A JPS58142627 A JP S58142627A
- Authority
- JP
- Japan
- Prior art keywords
- photocoupler
- gate
- circuit
- voltage
- gate circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/72—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
- H03K17/722—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region with galvanic isolation between the control circuit and the output circuit
- H03K17/723—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region with galvanic isolation between the control circuit and the output circuit using transformer coupling
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Thyristor Switches And Gates (AREA)
- Electronic Switches (AREA)
- Power Conversion In General (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 技術分野の説明
本発明は、低耐圧の光結合素子を使用してオンゲート電
流供給用トランジスタのスイッチングを可能とした自己
消弧形半導体素子のゲート回路に関するものである。Detailed Description of the Invention (a) Description of the Technical Field The present invention relates to a gate circuit for a self-extinguishing semiconductor device that enables switching of an on-gate current supply transistor using a low-voltage photocoupler. It is.
（ｂ） 従来技術の説明
従来のターンオフサイリスタ（以下、ＧＴＯと略称）の
ゲート回路を第１図につき説明すわけ、スイッチング電
源２は、パルストランスｌを介してノオン用のゲート電
流を供給す
るオンゲート回路１７、および該ＧＴＯ１６のターンオ
フ期間中、制御電極を負にバイアスするだめの負バイア
ス回路２１、にゲート畦カを供給する。オンゲート回路
１ ’７は、ダイオード３．４、平滑３ンデンサ７−に
より整紺、平滑化され、ＮＰＮトランジスタ１２のオン
、オフにより、抵抗体１３を介してオンゲート電流を供
給する。Ｎ Ｐ Ｎトランジスタ１２は、フォトカプラ
１１により与えられるベース信号により、オン、オフが
制御される。負バイアス回路２１は、ダイオード５，６
平滑コンデンサ８により整流平滑化され↓１（抗体１５
を介して０ＴＯ１６の制御ｎｆ、極を負にバイアスする
。ＧＴＯ１６は、第２図に示すゲート信号により制御さ
れる。オン指令が入ると、フォトノＪブラ１１を介して
ＮＰＮ トランジスタ１２にベース信号が与えらハ、オ
ンゲート電流が供給ざハる。(b) Description of the prior art The gate circuit of a conventional turn-off thyristor (hereinafter abbreviated as GTO) will be explained with reference to FIG. A gate ridge is provided to circuit 17 and to a negative bias circuit 21 for negatively biasing the control electrode during turn-off of the GTO 16. The on-gate circuit 1'7 is adjusted and smoothed by a diode 3.4 and a smoothing capacitor 7-, and supplies an on-gate current via a resistor 13 by turning on and off the NPN transistor 12. The N P N transistor 12 is controlled to be turned on or off by a base signal given by the photocoupler 11 . The negative bias circuit 21 includes diodes 5 and 6
Rectified and smoothed by smoothing capacitor 8 ↓1 (antibody 15
The control of 0TO16 via nf, biases the pole negatively. GTO 16 is controlled by a gate signal shown in FIG. When an ON command is input, a base signal is applied to the NPN transistor 12 via the photonograph 11, and an on-gate current is supplied.
ある一定時間オン指令出力後、フォトカプラ１１、トラ
ンジスタ１２のスイッチング時間を考慮し２て決定され
る時間Ｔｄ経過後、オフ指令が与えらね１、オフゲート
電流が供給される。After the ON command is output for a certain period of time, the OFF command is not given 1 and the OFF gate current is supplied after a time Td determined by considering the switching times of the photocoupler 11 and the transistor 12 has elapsed.
（）Ｔ？１６は、オフ指令に応じて、オフケート回路１
８により、パルストランス１９を介して与えられるオフ
ゲート’［流によりターンオフする。()T? 16 is an off-category circuit 1 in response to an off-command.
8, it is turned off by the off-gate current applied via the pulse transformer 19.
ＵＴＯｌ ６のゲート電極瞭カンード′岨極間インピー
ダンスは、オフゲート電流供給開始後も、 ＧＴＯ１６
がまだ導通している蓄積時間内においては、はぼインピ
ーダンス零であるが；”Ｇ’ｒ０１６がターンオフする
と、ゲート門標・□カソード電極間には、２０〜３０ｖ
程度の誘起逆ス゛パイク電圧が発生する。第３図は、こ
の時の等価回路である。第１図と同一部分には、同一の
符号を付して、その説１明を省略する。オフゲート電流
供給用のパルストランス１９は、図示の極性で出力電圧
■Ｐを発生している。ＧＴＯ１６０制御電極・陰極間に
は、配線のインダクタンス分２０との分圧によりＶＧＫ
なる誘起逆スパイク電圧が発生する。この時、トランジ
スタ１２はオフしているので、ｖＴｒなる寛、 圧が印
加される。又、同時に、フォトカプラ１１にはｖＴｒと
ほぼ同じＶＰＣなる電圧が印加さねる。The impedance between the gate electrodes of UTO16 remains the same even after off-gate current supply starts.
During the accumulation time when it is still conducting, the impedance is zero; however, when G'r016 is turned off, a voltage of 20 to 30 V is generated between the gate marker and the cathode electrode.
A certain amount of induced reverse spike voltage is generated. FIG. 3 shows an equivalent circuit at this time. Components that are the same as those in FIG. 1 are given the same reference numerals, and their description will be omitted. The pulse transformer 19 for supplying off-gate current generates an output voltage ■P with the polarity shown. VGK is applied between the GTO160 control electrode and the cathode due to the partial pressure with the wiring inductance of 20.
An induced reverse spike voltage is generated. At this time, since the transistor 12 is off, a voltage of vTr is applied. At the same time, a voltage VPC, which is approximately the same as vTr, is not applied to the photocoupler 11.
とこで、ｖＴ「、ＶＰＣは、コンデンサ７に充電された
オンゲート′電源′邂圧ＥＯＮＶｃｖｏＫが重畳して加
わる。すなわち、ＶＰＣ〜ＶＴｒ＝ＥＯＮ→−■。Ｋと
なる。Here, vT' and VPC are superimposed with the on-gate 'power supply' pressure EONVcvoK charged in the capacitor 7. That is, VPC~VTr=EON→-■.K.
□上述のように、オフゲート回路が作動する際、既にタ
ーンオフしているＮＰＮトランジスタ１２には、オンゲ
ート電源′電圧ＥｏＮと（） ＴＯ１６のオフ時に生じ
る誘起逆哀パイク′１圧が重畳するが、同時にフォトカ
プラ１１にもほぼ同じ・１圧が印加される。通常ＥｏＮ
は、１０〜ｌｏ数ｖ１■ＧＫは２０〜３０ｖであり、’
ＪＴｒ７ Ｖｐｃ＝ ３５〜４５ 、Ｖの電圧となる。□As mentioned above, when the off-gate circuit operates, the on-gate power supply' voltage EoN and the induced reverse pike'1 pressure that occurs when the TO16 is turned off are superimposed on the NPN transistor 12, which has already been turned off. Approximately the same voltage of 1 voltage is also applied to the photocoupler 11. Normal EoN
is 10~lo number v1■GK is 20~30v,'
JTr7 Vpc=35-45, the voltage is V.
トランジスタ１２、フォトカプラ１１の電圧定格は、印
加される螺圧の数倍のＩ割数を揚っものを選定するのが
一般である。The voltage ratings of the transistor 12 and the photocoupler 11 are generally selected to be several times the applied screw pressure.
しかし、市販のフォトカプラのコレクタ・エミッタ間電
圧定格は３０〜５０Ｖ以下のものが大半である。フォト
カプラに最大定格を越えた電圧が印加されるとフォトカ
プラ１１がブレークダウンしてフォトカプラの破損を招
いたり、トランジスタ１２がオンして、ＧＴＯ１６を誤
点弧させるという欠点があった。However, most commercially available photocouplers have collector-emitter voltage ratings of 30 to 50 V or less. If a voltage exceeding the maximum rating is applied to the photocoupler, the photocoupler 11 may break down, causing damage to the photocoupler, or the transistor 12 may turn on, causing the GTO 16 to fire incorrectly.
（Ｃ） 発明の目的
本発明は、上記欠点を除孝するためにｈされたものであ
り、制御極・＠榛間ｒｃｎ起される逆電圧か、オンケー
）を源に重畳する電路を形成しない位置に、フォトカプ
ラ素子を配置することによりフォトカプラのブレークダ
ウンになる該トランジスタの誤動作を防止することを目
的とする。(C) Purpose of the Invention The present invention was developed in order to eliminate the above-mentioned drawbacks, and does not form an electric circuit that superimposes the reverse voltage generated by the control pole @Hankuma rcn on the source. By arranging a photocoupler element at this position, the purpose is to prevent malfunction of the transistor that would result in breakdown of the photocoupler.
（ｄ） 発明の構成と作用
１ 納４図に本発明の実施例を示している。第１図と同
一部分には、同一符号を付してその説明は省略する。１
２はＰＮＰ？ランジスタで、抵抗体９を介してフォトカ
プラ１１により駆動される。第５図は、第３図に対応し
た等価回路である。ＧＩＩ’０１６０制御電極・陰極間
に発生する誘起逆スパイク＝、１７圧は、トランジスタ
１２のエミッタＥコレクタＣ間のみに重畳され、第４図
の如く該誘起電圧の重畳さ゛れない電路にあるフォトカ
プラ１１のエミッタ・コレクタ間には印加されないため
、フォトカプラの電圧定格は、オンゲー）１１（源電圧
Ｆｉ□Ｎ約十数■に対して選定すわばよく、電圧定格が
大幅に軽減される。(d) Structure and operation of the invention 1 Figure 4 shows an embodiment of the invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals, and their description will be omitted. 1
2 is PNP? It is a transistor and is driven by a photocoupler 11 via a resistor 9. FIG. 5 is an equivalent circuit corresponding to FIG. 3. GII'0160 The induced reverse spike generated between the control electrode and the cathode is superimposed only between the emitter E and the collector C of the transistor 12, and as shown in Fig. Since no voltage is applied between the emitter and collector of the photocoupler, the voltage rating of the photocoupler can be selected with respect to the source voltage Fi□N of about a dozen or so (on game) 11, and the voltage rating is significantly reduced.
（ｅ） 他の実施例 又、第６Ｍは本発明の他の実施例を示す回路図である。(e) Other examples Further, No. 6M is a circuit diagram showing another embodiment of the present invention.
第４図と同−及び同相当部分には同一の符号を付してい
る。抵抗体９を介してフォトカプラ１１により、ＰＮｐ
）ランジスタ１２１を駆動り、、ＮＰＮ）シンジスタ１
２を駆動するように構成することにより、前記実施例第
４図と同様の効果すなわち前記誘起逆スパイク嘔圧の重
畳の影響を受けないフ、ｔ−トカプラの作動が可能であ
る。The same reference numerals are given to the same and equivalent parts as in FIG. 4. PNp is connected via the resistor 9 by the photocoupler 11.
) drives transistor 121, ,NPN) synristor 1
2, it is possible to operate the t-to coupler with the same effect as in the embodiment shown in FIG. 4, that is, without being affected by the superimposition of the induced reverse spike and vomiting pressure.
（ｆ） 総合的な効果
以上、説明したように５本発明によれば、フォトカプラ
に印加される電圧は大幅に低減される故、低耐圧のフォ
トカプラの使用が可能となり、フォトカプラのブレーク
ダウンによるトランジスタの誤動作を防止できるなどの
実用的効果は大なるものである。(f) Overall effect As explained above, according to the present invention, the voltage applied to the photocoupler is significantly reduced, so it is possible to use a photocoupler with a low breakdown voltage, and the breakage of the photocoupler is reduced. This has great practical effects, such as being able to prevent malfunctions of transistors due to failure.
第１図は従来回路のゲート回路図、第２図、第３図は従
来回路の動作を説明する図、第４図は本発明の一実施例
を示す回路図、第５図は本発明を説明するだめの回路図
、第６図は本発明の他の実施例を示す回路図である。。
１・・・・パルストランス ２・・・スイッチンク酸源
３〜６・・・タイオード ７，８・・・平滑コンデン
サ９．１３．１５・・・ 抵抗体 １１・・・・フォト
カプラ１２．１２１・・・・・ トランジスタ１６・・
・ＧＴＯ
（７３１７） 代理人 弁理士 則 近 尉 佑 （０
、か１名）第１図
第２図
λ７晶八 ：
第３図
第４図
第５図
第６図Fig. 1 is a gate circuit diagram of a conventional circuit, Figs. 2 and 3 are diagrams explaining the operation of the conventional circuit, Fig. 4 is a circuit diagram showing an embodiment of the present invention, and Fig. 5 is a gate circuit diagram of a conventional circuit. FIG. 6 is a circuit diagram showing another embodiment of the present invention. . 1... Pulse transformer 2... Switching acid source 3 to 6... Diode 7, 8... Smoothing capacitor 9.13.15... Resistor 11... Photo coupler 12.121 ...Transistor 16...
・GTO (7317) Agent Patent Attorney Noriyuki Chika (0
, or 1 person) Figure 1 Figure 2 λ7 Shohachi: Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
たスイッチング素子を、光結合素子を介して駆動する自
己消弧形半導体素子のゲート回路において、前記自己消
弧形半導体素子の制御極・罐極間に誘起される逆スパイ
ク颯圧が前記直流４源Ｖこ重畳する電路を形成しない位
置に、前記光結合素子を配置したことを特徴とする自己
消弧形半導体素子のゲート回路。In a gate circuit for a self-arc-extinguishing semiconductor element that drives a switching element provided between a DC source and a control pole of the self-arc-extinguishing semiconductor element via an optical coupling element, A gate of a self-extinguishing type semiconductor device, characterized in that the optical coupling device is disposed at a position where a reverse spike pressure induced between a control pole and a housing pole does not form an electric path where it is superimposed on the four direct current sources V. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57023553A JPS58142627A (en) | 1982-02-18 | 1982-02-18 | Gate circuit of self arc extinction type semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57023553A JPS58142627A (en) | 1982-02-18 | 1982-02-18 | Gate circuit of self arc extinction type semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58142627A true JPS58142627A (en) | 1983-08-24 |
| JPH0352256B2 JPH0352256B2 (en) | 1991-08-09 |
Family
ID=12113679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57023553A Granted JPS58142627A (en) | 1982-02-18 | 1982-02-18 | Gate circuit of self arc extinction type semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58142627A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63102334U (en) * | 1986-12-23 | 1988-07-04 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5465466A (en) * | 1977-11-04 | 1979-05-26 | Hitachi Ltd | Control circuit for thyristor |
-
1982
- 1982-02-18 JP JP57023553A patent/JPS58142627A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5465466A (en) * | 1977-11-04 | 1979-05-26 | Hitachi Ltd | Control circuit for thyristor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63102334U (en) * | 1986-12-23 | 1988-07-04 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0352256B2 (en) | 1991-08-09 |
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