JPS58138325U - Composite laminated ceramic capacitor - Google Patents

Composite laminated ceramic capacitor

Info

Publication number
JPS58138325U
JPS58138325U JP3440682U JP3440682U JPS58138325U JP S58138325 U JPS58138325 U JP S58138325U JP 3440682 U JP3440682 U JP 3440682U JP 3440682 U JP3440682 U JP 3440682U JP S58138325 U JPS58138325 U JP S58138325U
Authority
JP
Japan
Prior art keywords
ceramic capacitor
laminated ceramic
composite laminated
external electrodes
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3440682U
Other languages
Japanese (ja)
Inventor
輝幸 池田
嶋田 勇三
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP3440682U priority Critical patent/JPS58138325U/en
Publication of JPS58138325U publication Critical patent/JPS58138325U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は帰還回路を有する増幅器でコンデンサ応用例を
示す図、第2図は発振回路での9ンデンサ応用例を示す
図、第3図はロータリースイッチを利用したコンデンサ
の切換え回路図、第4図は本考案の一実施例を示す内部
電極パターンを付した生シートの平面図、第5図は2°
n比で構成させるためのシートの積層例を示す斜視図、
第6図は焼結した後の外部電極の配置例を示す斜視図、
第7図は他の実施例の内部電極パターンを付した生シニ
トの平面図、第8図は第7図の内部電極パターンを有す
る2nn比で構成させるためのシートの積層例を示す斜
視図、第9図は焼結した。後の  −外部電極の配置例
を示す斜視図、第10図はリード線対は及び外装仕上げ
を施こした外観図、第11図は1ステツプ2°の電極の
持つ容量で可変させるための′ロータリースイッチ接続
配線図である。 図にiいて、40・・・焼結前の生シート、42〜46
・・・内部電極パターン、47・・・とり出し電極、5
1・・・共通電極層、52〜55・・・パターン43〜
46を持つ生シート、61〜64・・・外部電極、71
・・・焼結前の生シート、72・・・とり出し電極、7
3〜76・・・Znn比の面積を持つ内部電極パターン
、81及び82・・・パターン73〜76を持つ生シー
ト、91〜95・・・外部電極、101〜105・・・
リード線、106・・・外装仕上げ、111・・・本考
案の複合積層セラミックコンデンサ、112・・・ロー
タリースイッチ。
Figure 1 shows an example of a capacitor application in an amplifier with a feedback circuit, Figure 2 shows an example of a 9-capacitor application in an oscillation circuit, Figure 3 is a capacitor switching circuit diagram using a rotary switch, and Figure 4 shows an example of a capacitor application in an oscillation circuit. The figure is a plan view of a green sheet with an internal electrode pattern showing an embodiment of the present invention, and Figure 5 is a 2°
A perspective view showing an example of laminating sheets to be configured with an n ratio,
FIG. 6 is a perspective view showing an example of the arrangement of external electrodes after sintering;
FIG. 7 is a plan view of raw Shinito with an internal electrode pattern according to another embodiment, and FIG. 8 is a perspective view showing an example of laminating sheets to be constructed with a 2nn ratio having the internal electrode pattern of FIG. 7. Figure 9 shows sintered. Figure 10 is a perspective view showing an example of the arrangement of the external electrodes, Figure 10 is an external view of the lead wire pair and the exterior finish, and Figure 11 is a diagram showing the arrangement of the external electrodes. It is a rotary switch connection wiring diagram. In the figure, 40...Raw sheet before sintering, 42-46
...Internal electrode pattern, 47...Takeout electrode, 5
1... Common electrode layer, 52-55... Pattern 43-
Raw sheet with 46, 61-64...external electrode, 71
... Raw sheet before sintering, 72 ... Take-out electrode, 7
3-76... Internal electrode pattern with area of Znn ratio, 81 and 82... Raw sheet with patterns 73-76, 91-95... External electrode, 101-105...
Lead wire, 106...Exterior finish, 111...Composite multilayer ceramic capacitor of the present invention, 112...Rotary switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 1つのチップに複数の外部電極を設け、少なくとも前記
外部電極の1つを共通電極とし、かつこの共通電極と、
他の外部電極との間の容量比を1゜2、 4. 8・・
・2” nの比で得られるように内部電極パターンを接
続したことを特徴とする複合積層セラミックコンデンサ
A plurality of external electrodes are provided on one chip, at least one of the external electrodes is a common electrode, and this common electrode,
Capacitance ratio with other external electrodes is 1°2, 4. 8...
- A composite multilayer ceramic capacitor characterized by internal electrode patterns connected to obtain a ratio of 2"n.
JP3440682U 1982-03-11 1982-03-11 Composite laminated ceramic capacitor Pending JPS58138325U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3440682U JPS58138325U (en) 1982-03-11 1982-03-11 Composite laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3440682U JPS58138325U (en) 1982-03-11 1982-03-11 Composite laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JPS58138325U true JPS58138325U (en) 1983-09-17

Family

ID=30045889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3440682U Pending JPS58138325U (en) 1982-03-11 1982-03-11 Composite laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JPS58138325U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9036330B2 (en) 2009-03-17 2015-05-19 Samsung Electro-Mechanics Co., Ltd. Multilayer chip capacitor and method of fabricating the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4829737B1 (en) * 1969-09-05 1973-09-13
JPS5494654A (en) * 1978-01-06 1979-07-26 Suwa Seikosha Kk Step variable condenser

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4829737B1 (en) * 1969-09-05 1973-09-13
JPS5494654A (en) * 1978-01-06 1979-07-26 Suwa Seikosha Kk Step variable condenser

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9036330B2 (en) 2009-03-17 2015-05-19 Samsung Electro-Mechanics Co., Ltd. Multilayer chip capacitor and method of fabricating the same

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