JPS58137294A - Method of producing electrically mutually connecting package - Google Patents

Method of producing electrically mutually connecting package

Info

Publication number
JPS58137294A
JPS58137294A JP57018132A JP1813282A JPS58137294A JP S58137294 A JPS58137294 A JP S58137294A JP 57018132 A JP57018132 A JP 57018132A JP 1813282 A JP1813282 A JP 1813282A JP S58137294 A JPS58137294 A JP S58137294A
Authority
JP
Japan
Prior art keywords
conductor
multilayer
package
wiring board
predetermined pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57018132A
Other languages
Japanese (ja)
Inventor
功 西村
石　一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57018132A priority Critical patent/JPS58137294A/en
Publication of JPS58137294A publication Critical patent/JPS58137294A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は半導体パッケージの製造方法に係シ、更に具体
的に云えば、好ましくは半導体装置の一体的装着に適し
た多層配線基板の電気的相互接続パッケージの製造方法
に係るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor package, and more particularly to a method of manufacturing an electrical interconnection package of a multilayer wiring board, preferably suitable for integral mounting of semiconductor devices. This is related.

回路装置のＬＳＩ化、高性能化に伴い、関連回路に要求
される性能に適合する電気的相互接続パッケージを得る
ことが必要とされている。2. Description of the Related Art As circuit devices become more integrated and more sophisticated, it is necessary to obtain electrical interconnection packages that meet the performance requirements of related circuits.

上記問題の解決手段として、配線を厚膜印刷焼結方式で
形成し、基材および層間絶縁物としてアルミナセラミツ
ンヲ用い多層化し形成されたセラミックパッケージの上
面に複数の集積回路チップ管ボンティングすることによ
って半導体素子への相互接続のための高密度および高性
能の多鳩基板が用いられている。しかしながら、この方
法は配線密度が印刷工程の精度で限定されるため大容量
配線の要求に対しては多層化が史に進むことになシ多く
の実際的問題を生じ、特に層数の増大は各層間の接続点
数を大幅に増やすため、製造歩留の大幅な低下をもたら
すという問題がある。As a solution to the above problem, wiring is formed using a thick film printing and sintering method, and multiple integrated circuit chip tubes are bonded to the top surface of a multilayered ceramic package using alumina ceramic as the base material and interlayer insulator. This has led to the use of high density and high performance multi-domain substrates for interconnection to semiconductor devices. However, since the wiring density of this method is limited by the precision of the printing process, it is difficult to increase the number of layers in response to the requirements for large-capacity wiring.This method causes many practical problems, especially when increasing the number of layers. Since the number of connection points between each layer is significantly increased, there is a problem in that the manufacturing yield is significantly reduced.

上記問題の異なる解決手段として耐火性の（例えばアル
ミナ）基板上に複雑な薄膜相互パッケージ會製造するこ
とによって、即ち基板上に複数のガラス層を形成し、付
着された各ガラス層上に複数の薄膜導体パターンを付着
し、種々の導体ノ（ターン相互間の電気的相互接続のた
めの垂直方向導体スタッドを選択的に付着し、形成され
たガラスパッケージの上面に複数の集積回路チップｔボ
ンディングすることによシ半導体素子への相互接続のた
めの多層基板を形成するという方法があるが、ガラスの
取扱いに於いては焼成温度が重要な要素であシ、導体層
の下の破壊を防ぐために紘ガラスの焼結温度を充分考慮
に入れる必要がある。°焼結温度は下のガラス層を軟化
させて粘性変形を生ぜしめ、導体パターンの変位を生せ
しめる危険を伴う。A different solution to the above problem is to fabricate a complex thin-film interpack on a refractory (e.g. alumina) substrate, i.e. by forming multiple glass layers on the substrate and with multiple layers on each deposited glass layer. Depositing thin film conductor patterns, selectively depositing vertical conductor studs for electrical interconnection between various conductor turns, and bonding a plurality of integrated circuit chips to the top surface of the formed glass package. Firing temperatures are an important factor in handling glass, especially to form multilayer substrates for interconnection to semiconductor devices, to prevent breakdown of the conductive layers below. It is necessary to take into account the sintering temperature of the glass.° The sintering temperature softens the underlying glass layer and causes viscous deformation, with the risk of causing displacement of the conductor pattern.

また、ガラスに亀裂を生せしめる危険も存在し、多層セ
ラミック構成素子と多層ガラス構成素子との関に於ける
熱膨張係数が厳密に適合する必要がある、などパッケー
ジの一体性を損う欠点がめシ製造においては多大の配慮
を要するという問題がある。There is also the risk of cracking the glass, and there are drawbacks that compromise the integrity of the package, such as the need to closely match the coefficients of thermal expansion between the multilayer ceramic and multilayer glass components. There is a problem in that manufacturing requires a great deal of consideration.

本発明の目的は、半導体装置への相互接続を達成する多
層配線基板の電気的相互接続パッケージの製造方法を提
供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing an electrical interconnection package for a multilayer wiring board that achieves interconnection to a semiconductor device.

本発明の他の目的は厚膜導体層の多層分布を含む予め形
成された基板上に、薄□膜導体層の多層分布を含む予め
形成された基板を、先に形成された基板の導体層に歪み
を生じることなく形成し得る多層配線基板の電気的相互
接続パッケージを提供することにある。Another object of the present invention is to place a preformed substrate comprising a multilayer distribution of thin film conductor layers on a preformed substrate comprising a multilayer distribution of thick film conductor layers. An object of the present invention is to provide an electrical interconnection package for a multilayer wiring board that can be formed without causing distortion.

本発明の更に他の目的紘、歩留の良い多層配線基板の電
気的相互接続パッケージの製造方法を提供することにあ
る。Still another object of the present invention is to provide a method for manufacturing an electrical interconnection package for a multilayer wiring board with high yield.

本発明の特黴紘、所定のパターンを有する多層配線基板
上に、予め形成された多層分布の導体層を含み所定のパ
ターンを有する配線基板を、夫々の所定のパターンの相
互接続が行われる様に、複数の導電性が良好な磁性体を
、磁力によシ、所定の位置に選択的に配置することによ
って容易に相互接続を行ない、歩留シの良い所望の電気
的相互接続パッケージを得ること４ＣＴｏる。The feature of the present invention is to provide a multilayer wiring board having a predetermined pattern on which the wiring board includes a multi-layered conductor layer formed in advance, and a wiring board having a predetermined pattern, such that interconnection of each predetermined pattern is performed. By selectively placing a plurality of highly conductive magnetic materials in predetermined positions by magnetic force, interconnections can easily be made to obtain a desired electrical interconnection package with high yield. That's 4CToru.

次に、図面を参照して、本発明について詳細に説明する
。第１図、第２図および第３０社、外部から複数のピン
１０を経て複数のチップ位１ｉ１１２に接続される必要
のある複雑な相互接続構造体の構造を詳細に示している
。複数のチップ１４が各チップの位置１２に配置される
。キャパシタ１８の如き構成素子はパッケージの周辺に
容易に装着される。第２図に於てよシ詳細に示されてい
る厚膜相互接続導体層は電圧分配プレーン、接地プレー
ン、ｘ−Ｙ信号プレーン、および電圧再分配プレーンを
構成している。Next, the present invention will be described in detail with reference to the drawings. 1, 2 and 30 show in detail the construction of a complex interconnect structure that needs to be externally connected via a plurality of pins 10 to a plurality of chip locations 1i112. A plurality of chips 14 are placed at each chip location 12. Components such as capacitor 18 are easily mounted around the periphery of the package. The thick film interconnect conductor layers, shown in greater detail in FIG. 2, constitute voltage distribution planes, ground planes, x-y signal planes, and voltage redistribution planes.

この実施例に於ては多層配線上部構造体即ち峰ジュール
頷が、予め形成された多層セラミック基板２２に結合さ
れている。多層セラミック基板ｎ。In this embodiment, a multilayer wiring superstructure or ridge is bonded to a preformed multilayer ceramic substrate 22. Multilayer ceramic substrate n.

下面に配置されたパッド冴はニッケルめっきされたタン
グステン金属がらなシ、ピンｌＯがろう付けによシ結合
されている。The pad located on the bottom surface is made of nickel-plated tungsten metal, and a pin 10 is connected to it by brazing.

多層セラミック基板２２社複数の導体プレーンかを含ん
でいる。更に垂直方向の導体路が、金属で充填され九複
数の貫通孔２８によシ設けられている。多層セラミツク
基板２２拡電圧分配プレーンを設けるように働く。電圧
プレーンの数はチップの回路論理ファミリの電圧条件に
よって決定される。22 multilayer ceramic substrates contain multiple conductor planes. Furthermore, vertical conductor tracks are provided through nine through holes 28 filled with metal. Multilayer ceramic substrate 22 serves to provide an expanded voltage distribution plane. The number of voltage planes is determined by the voltage requirements of the circuit logic family of the chip.

又、多層セラミック基板２２には外ｓ４の１ｉ！貌を行
なうピン１０が第３図に概略的に示される複数個のパッ
ド（資）のような半導体チップレベルの格子よりも大１
！′＆格子を形成しているために必要とされる相互接続
の中継を行う。又、第３図はモジュール加の上面に配置
された複数のパッドあから複数の導体路あへ容易に相互
接続が行なわれることを示している。導体路あは金属付
着工程によって形成されるが、上面への接続はワイヤポ
ンディング、熱圧着等によって達成され得る。In addition, the multilayer ceramic substrate 22 has an outer s4 1i! The pins 10 that carry out the configuration are larger than the semiconductor chip level grid, such as the plurality of pads shown schematically in FIG.
! '& performs the interconnection relays required to form the lattice. FIG. 3 also illustrates the ease with which interconnections can be made from a plurality of pads disposed on the top surface of the module to a plurality of conductor tracks. The conductor tracks are formed by a metal deposition process, but connections to the top surface can be accomplished by wire bonding, thermocompression bonding, etc.

モジュール２０紘複数の絶縁性セラミック層菊によシ分
離されている複数のレベル即ちプレーンに配置された導
体領域蕊を含んでいる。異なるレベル間の垂直方向の相
互接続を複数の導体路４４に：よシ行っている。又、モ
ジュール加と多層セラミック基板だとの間の垂直方向の
相互接続は複数の導電性の良好な磁性体８０によ〕達成
される。第２図に於て最上レベルの導体層弱が、示され
ている。最上レベルの導体層栃は第３図に示されている
ノくラドあ及び導体路謁に対応する。半導体チップ１４
は、導体５２及びはんだ接続部具によや画定Ｏ導体路に
結合されている。Module 20 includes conductor regions arranged in a plurality of levels or planes separated by a plurality of insulating ceramic layers. Vertical interconnections between different levels are provided by a plurality of conductor tracks 44. Also, vertical interconnection between the module module and the multilayer ceramic substrate is achieved by a plurality of highly conductive magnetic bodies 80. In FIG. 2 the top level conductor layer is shown. The top level conductor layer corresponds to the slots and conductor paths shown in FIG. semiconductor chip 14
is coupled to the conductor 52 and the solder connection to the defined O conductor path.

技術変更を可能とするために、最上レベルの導体層４６
を形成するパッド３４ｔＣｔｉ１３図に図示の如く技術
変更パッド団が設けられている。従って／（ラドＵと技
術変更）くラド郭を接続している導体路蕊を機械的又は
レーザ切断方法により切断し、ワイヤボンディングの如
き他の接続を行なうことによって、技術変更が行なわれ
る。Top level conductor layer 46 to allow for technology changes
Pads 34tCti13 forming a pad 34tCti13 are provided with a group of technology-changed pads as shown in the figure. Therefore, a technological change is made by cutting the conductor tracks connecting the rads by mechanical or laser cutting methods and making other connections such as wire bonding.

第４図（２）〜第４図（ト）は第１図及び第２図に於て
一般的に加及びｎとして示されている多層配線基板を夫
々１００及びωとして表わし、これらを導体片（ａ性体
）ＳＯによシ、磁力を利用して第４図（ロ）及び第４図
＠に示す如く相互接続し第２［Ｕｒｃ図示の如き電気的
相互接続パッケージを製造するための本発明による実施
例を赤している。4(2) to 4(g) represent the multilayer wiring boards generally shown as 100 and ω in FIGS. 1 and 2 as 100 and ω, respectively. (A-type body) SO is used to interconnect the package as shown in Figures 4(b) and 4@ using magnetic force, and the second [Urc] The embodiment according to the invention is shown in red.

第４図（４）に図示の如く、金属で充填された導電性貫
通孔６２及び多層分布を含む導体層圀を有する予め形成
されたセラミック基板φに所定のノ（ターン状に接続さ
れるべき複・数の接続）（ット°６を設ける。しかるの
ちに、複数のｉｌ続）くツドレペルの格子よりも小さな
格子に並べられた電磁石群７０の複数の振枕パッド槌と
対応する位置７１のみに電流等を流したりして磁力を発
生させ上部多層構遺基装置７１に次いで吸着導体片（資
）をセラミック基板ωの接続パッド田に近づけ、位置を
調整し接続パッド田と導体片（資）を第４図（Ｑの如く
密着させる。As shown in FIG. 4(4), a pre-formed ceramic substrate φ having a conductive through-hole 62 filled with metal and a conductor layer field including a multilayer distribution is connected in a predetermined turn shape. Positions 71 corresponding to the plurality of swing pillow pad hammers of the electromagnet group 70 arranged in a grid smaller than the grid of the tsudrepel. A magnetic force is generated by passing a current or the like through the upper multilayer structure base device 71, and then the adsorbing conductor piece (material) is brought close to the connection pad field of the ceramic substrate ω, the position is adjusted, and the connection pad field and the conductor piece (material) are brought close to each other. 4 (Q).

導体片（資）は磁性体で６９導電性の艮好なニッケル等
を用いる。導体片（資）には第４幽囚に図示の如くはん
だ８１などをめっきし用いてもよい。第４幽＠に示す如
く電磁石群７０の個々の電磁石７１　、７２は複数の接
続パッド６の格子よシも小さい格子で並べらｎているた
め導体片（資）がｒａ接して吸着されることはない。ま
た、導体片（資）に対しては磁力縁（イ）が同一方向に
発生せしめるように個々の電磁石を操作することによ）
最も近い導体片同志の短絡を防ぐ。The conductor piece is made of a magnetic material such as 69 conductive nickel. The conductor piece (material) may be used by plating the fourth capacitor with solder 81 as shown in the figure. As shown in the fourth column, the individual electromagnets 71 and 72 of the electromagnet group 70 are arranged in a grid that is smaller than the grid of the plurality of connection pads 6, so that the conductor pieces (materials) are attracted to each other in contact with each other. There isn't. In addition, by operating the individual electromagnets so that the magnetic force edge (A) is generated in the same direction with respect to the conductor piece (I).
Prevent short circuits between the nearest conductor pieces.

前記又第４図（０に図示の如く、導体片帥を接続パッド
６５ＩＩＣ密着させたのち、セラミック基板の接続パッ
ド印の面と反対の面よシ導体片（資）が接続パッド団に
密着するよう電磁石７５を第４図（Ｑに点１で示す如く
働かせる。このとき、電磁石群７０よυの磁力を消滅さ
せることが望ましい。電磁石７５によｐ導体片（資）を
密着させたのち電磁石群７０を取）去る。As shown in FIG. 4 (0), after the conductor strip is brought into close contact with the connection pad 65IIC, the conductor strip (material) is brought into close contact with the connection pad group from the side opposite to the surface of the ceramic substrate with the connection pad mark. The electromagnet 75 is operated as shown by point 1 in FIG. Take group 70).

次いで、第４図（ロ）に図示の如き、多層分布を含む導
電層％と垂直方向の相互接続を行なう導電路９２を有す
るセラミック基板槙に所定のパターンを形成するべき複
数の接続パッド％を設け、対応する導体片圀に同一に図
示の如く位置を合せたのち、導体片（資）を溶融させ基
板ωと基板１００の電気的相互接続を第４口部に図示の
如く行なう。Next, as shown in FIG. 4(b), a plurality of connection pads to form a predetermined pattern are placed on a ceramic substrate having a conductive layer including a multilayer distribution and a conductive path 92 for vertical interconnection. After installing and aligning the corresponding conductor strips in the same manner as shown in the figure, the conductor pieces are melted to establish electrical interconnection between the substrate ω and the substrate 100 at the fourth opening as shown in the figure.

しかるのち半導体チップ１４をはんだ溶融接続法により
接続することによシ第４図（ト）に図示の如き所望の電
気的相互接続パッケージを得る。The semiconductor chips 14 are then connected by a solder fusion process to obtain the desired electrical interconnection package as shown in FIG. 4(g).

モジュールｎはセラミック基板に限られることはなく、
・薄膜多層基板によシ配線密度の増加を図ったものでも
よい。Module n is not limited to ceramic substrates,
- A thin-film multilayer substrate with increased wiring density may also be used.

この実施例に示す様に、本発明の、所定のパターン団を
有する多層配線基板６０　（２２）上に、予め形成され
た多層分布の導体層拐を含み所定のパターン９５を有す
る配線基板１００（イ）を、夫々の所定のパターンの相
互接続が行われる様に、複数の導電性が良好な磁性体帥
を、磁力によシ、所定の位置７１に配置することによっ
て容易に相互接続を行い、歩留りの良い所望の電気的相
互接続パッケージを製造する仁とができる。As shown in this embodiment, a wiring board 100 (22) of the present invention having a predetermined pattern 95 including conductor layer strips with a multilayer distribution formed in advance is placed on a multilayer wiring board 60 (22) having a predetermined pattern group. (a) can be easily interconnected by placing a plurality of magnetic conductive layers at predetermined positions 71 using magnetic force so that interconnections in respective predetermined patterns are performed. It is now possible to manufacture desired electrical interconnect packages with high yield.

斯くて、本発明の製造方法を用いれば、容易に歩留りの
良い電気的相互接続パッケージを実現できる。Thus, by using the manufacturing method of the present invention, electrical interconnect packages with high yield can be easily realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は単一基板上の複数個の半導体チップを相互接続
するための半導体集積回路パッケージを示す斜視図であ
υ、第２口拡第１図の１ｉｌＡ−にに於ける部分的断面
図であって、パッケージのための多レベルの相互接続を
よル詳細に示している。 第３図は上面の導体路に特定のチップを相互接続する方
法を示ｔ／４１図に於ける単一チップ位置の／ 拡大図でｔ）シ′・第４図（４）乃至第４図（ト）は相
互接続パッケージを製造するための本発明による一実施
例に於ける一連の工程を示す概略的断面図である。 １０・・・ピン、１２・・・チップ位置、１４・・・半
導体チップ、１８・・・キャパシタ、加・・・多層配縁
モジュール％２２゜６０　、１００・・・セラミック基
板、郭・・・技術変更パッド、７０・・・電磁石群、（
資）・・・導体片（磁性体）、（イ）・・・磁力線、７
５・・・電磁石、６５．８５・・・接続パッド。 代理人　弁通士　　秋　本　正　実 第１図 ０ 第２図 第３図 第４図　（Ａ） 第４因ＣＢ） 第４図　（Ｃ）FIG. 1 is a perspective view showing a semiconductor integrated circuit package for interconnecting a plurality of semiconductor chips on a single substrate. , which shows in greater detail the multi-level interconnections for the package. Figure 3 shows how to interconnect a particular chip to the top surface conductor tracks. FIG. 6(g) is a schematic cross-sectional view showing a series of steps in an embodiment of the present invention for manufacturing an interconnect package. 10...Pin, 12...Chip position, 14...Semiconductor chip, 18...Capacitor, Addition...Multilayer wiring module%22゜60, 100...Ceramic substrate, enclosure... Technology change pad, 70...Electromagnet group, (
Capital)...Conductor piece (magnetic material), (A)...Magnetic field lines, 7
5... Electromagnet, 65.85... Connection pad. Agent Attorney Tadashi Akimoto Figure 1 0 Figure 2 Figure 3 Figure 4 (A) 4th cause CB) Figure 4 (C)

Claims (1)

【特許請求の範囲】[Claims] 所定のパターンを有する多層配線基板上に、予め形成さ
れた多層分布の導体層を含み所定のパターンを有する配
線基板を、夫々の所定のパターンの相互接続が行われる
様に、複数の導電性が良好な磁性体ｔ１磁力によシ、所
定の位置に配置して、接続を行うことを特徴とする電気
的相互接続パッケージの製造方法。A wiring board having a predetermined pattern including preformed multilayer distribution conductor layers is placed on a multilayer wiring board having a predetermined pattern so that a plurality of conductive layers are connected to each other in a predetermined pattern. A method of manufacturing an electrical interconnection package, characterized in that the connection is made by placing a magnetic substance in a predetermined position using a good magnetic force.
JP57018132A 1982-02-09 1982-02-09 Method of producing electrically mutually connecting package Pending JPS58137294A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57018132A JPS58137294A (en) 1982-02-09 1982-02-09 Method of producing electrically mutually connecting package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57018132A JPS58137294A (en) 1982-02-09 1982-02-09 Method of producing electrically mutually connecting package

Publications (1)

Publication Number Publication Date
JPS58137294A true JPS58137294A (en) 1983-08-15

Family

ID=11963074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57018132A Pending JPS58137294A (en) 1982-02-09 1982-02-09 Method of producing electrically mutually connecting package

Country Status (1)

Country Link
JP (1) JPS58137294A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02119164A (en) * 1989-09-20 1990-05-07 Hitachi Ltd Semiconductor module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02119164A (en) * 1989-09-20 1990-05-07 Hitachi Ltd Semiconductor module
JPH0544190B2 (en) * 1989-09-20 1993-07-05 Hitachi Ltd

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