JPS58128755A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58128755A
JPS58128755A JP1004582A JP1004582A JPS58128755A JP S58128755 A JPS58128755 A JP S58128755A JP 1004582 A JP1004582 A JP 1004582A JP 1004582 A JP1004582 A JP 1004582A JP S58128755 A JPS58128755 A JP S58128755A
Authority
JP
Japan
Prior art keywords
terminal
case
substrate
inner lead
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1004582A
Other languages
Japanese (ja)
Inventor
Haruo Yamanaka
山中　晴夫
Yoshihiko Tojo
義彦 東條
Shuji Sugioka
杉岡　修次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1004582A priority Critical patent/JPS58128755A/en
Publication of JPS58128755A publication Critical patent/JPS58128755A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To contrive reduction in the number of manufacturing processes and the time required for the resin sealing of the titled semiconductor device by a method wherein the sealing is performed by filling a bonding material up to the point in the vicinity of the upper end of a case. CONSTITUTION:A substrate 11, whereon a hybrid integrated circuit is formed, is placed on and adhered to the substrate-placing part 10 of the case 9, and the inner lead 12 coming out of the substrate 11 and the inner lead 14 from a terminal 13 are connected. After Si resin 15, which protects the substrate 11, has been injected and hardened, the leads 12 and 14 are fixed by filling a filler 16 up to the top of the terminal 13 which was provided at the aperture edge of the case 9, and at the same time, the case 9 and the terminal 13 are adhered. As a result, not only a lid is unnecessitated, but also the number of adhesion can be reduced, it gives the better external appearance, and the time required for resin sealing can also be cut down.

Description

【発明の詳細な説明】 発明の技術分野 本発明は半導体ａｔに俤り、物にｍ＊糸槓囲躇が両正さ
れた半導体ｗｉｔの改真に−する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention extends to a semiconductor AT and to a modification of a semiconductor WIT in which an m* thread enclosure is corrected.

発明のａ術的背景と七の閾ｍ点 健米より混成集槓鴎ｍを封止する方法としては、例えば
第１−に示すように、ケース１内の基板棋［１１２上に
１成ＩＩＩＩ楓回躇が形成された基板３を載置して接層
し、ケース１と端子ターミナル４を撤着した後、基板３
上の本号とコンタクトしニーるインナー・リード５と端
子ターミナル４からのインナー・リード６とを砿枕して
ｊｋｌＬ３を保−するゲル状のシリコン＠馳１を江人し
硬化させる。From the technical background of the invention and the method of sealing the hybrid Shukokum from the seven threshold m point Kenmai, for example, as shown in No. 1, After mounting and bonding the board 3 on which the mapped circuit is formed, and removing the case 1 and the terminal terminal 4, the board 3
The inner lead 5 that is in contact with the main part above and the inner lead 6 from the terminal terminal 4 are covered with gel-like silicone 1, which holds the jklL3, and hardened.

次いでフタ８を端子ターミナル４に嶺膚して貞麿封止す
るものがめる。Next, the lid 8 is attached to the terminal terminal 4 to seal it.

ところでこの封止でｕｕＴｈｍ＆３とケース１、ケース
１と亀子ターミナル４、端子ターミナル４とフタＳの３
ＭＭと、依盾回畝が多く嵌着にはその郁Ｉｆ像ｗ剣の波
化を責するなど時間もかかり、さらに接ｙ１１剤のはみ
出しによる側御バリが健生し外−が愚くなる一点もめっ
た。また徴膚銅のｍ布にもｙＩ＃１Ｋを賛求され、袈遺
工嶺の１鯛化が困欅でめった＠ ＠明の目的 本発明はかかる従来の一点な解消するためになされたも
ので、接層のｌ！ａｌ畝と装置時間とを減らした半４体
！４に直を提供することｔｌ的とする。By the way, with this sealing, uuThm&3 and case 1, case 1 and Kameko terminal 4, terminal terminal 4 and lid S 3
With MM, there are a lot of ridges and it takes time to fit, as the Iku If statue w sword becomes wavy, and the side burrs due to the protrusion of the y11 agent become healthy, making the outside look stupid. I struggled. In addition, yI #1K was approved for the m-cloth of Chong copper, and it was difficult and rare to convert the kei-kunrei into a single sea bream. So, the tangential l! 4 halves with reduced al ridges and equipment time! It is important to provide direct access to 4.

発明の概要 不発明は上端にターミナルが配設されたケース内Ｋｍ成
集槓回路が形成された基板を接着剤を介して固定し、１
基板の上に保Ｓ郁材膚を形成して前記置成巣棟圓略が樹
上される半導体装置において、前記保ｍ郁材層は前記ケ
ースＯ上端近傍まで形成され九シリコーン稠脂層および
この上に前１ターミナ羨の上端まで形成された嵌嵩ＭＷ
Ｉとからなること４１−％似とする。Summary of the invention The invention is based on a case in which a terminal is arranged at the upper end, and a board on which a Km integrated circuit is formed is fixed via an adhesive.
In a semiconductor device in which a protective material layer is formed on a substrate to form the above-mentioned structure, the protective material layer is formed up to the vicinity of the upper end of the case O, and includes a silicone resin layer and a silicone resin layer. On top of this, an inset MW is formed up to the upper end of the front 1st terminus.
The fact that it consists of I is assumed to be 41-% similar.

＠明ｏ＊１ｉｉｓｓ 以下本発明を図面にもとづき詳細に説明する。@akio*1iiss The present invention will be explained in detail below based on the drawings.

纂２−は本楯−による半導体装置を示した−のでめる。Series 2 shows a semiconductor device based on the present invention.

ケース稙円の基＆−を藝１０に偽成集秋１ｇ１魔が形成
された基板１１を載置し１黴着し、基＆１１から出るイ
ンナー・リード１２と端子ターミナル１３からのインナ
ー・リード１４とｔ接続し′ｃＩＤる◎そして麺板１１
＆−保一するゲル状のシリコン掬繍１５をケースＢの開
口端（上端ン近傍筐で注入して愼化壜＜た愼、ケース９
の開口端に配設された電子ターミナル１３の上端までシ
リコーン＠廁、エポキシ＠ｍＩ等の蝋層剤１らを充填し
て、インナー・リード１２．１４４Ｉ：固定すると共に
、ケースＳと端子ターミナル１３とを艦層しである。Place the circuit board 11 on which the fake mold is formed on the base &- of the case base 10, and attach the inner lead 12 coming from the base &11 and the inner lead 14 coming from the terminal terminal 13. Connect with 'cID' ◎ and noodle board 11
&- Inject the gel-like silicone 15 into the opening end of case B (near the upper end) to form a bottle, case 9.
The inner lead 12.144I: is fixed, and the inner lead 12.144I: is fixed, and the case S and the terminal terminal 13 are filled with a wax layer agent 1 such as silicone, epoxy, etc. to the upper end of the electronic terminal 13 disposed at the open end of the terminal. It is a ship layer.

このよりにケース８の開口端にＥ設されｆｃ端子ターン
ナルの上１ｍまで憾嬢剤１６を尤横して樹上することに
＋よｉ）、ｍ＆１１とコンタクトした４ノナ−・リード
１２と端子ターミナル１３とを接着するので、７り・（
第１図）が不資となるばかやでなく振ｌ＃回畝もへり徴
膚剤のはみ出しがなくなりＩＡｇＩＩＭもよくなり用貴
時闇が短輪される。As a result, it is possible to place the retarder 16 at the open end of the case 8 up to 1 m above the fc terminal turnall (+i), and connect the 4-non-lead 12 and the terminal in contact with m&11. Terminal 13 is glued, so 7ri・(
(Fig. 1) is no longer a waste of money, the ridges and dermatitis are no longer protruding, and the IAgIIM is also improved, and the darkness is shortened.

筐た、第３〜４図は他の爽抛ガをボしたもので、ケース
ＩＴと端子ターミナル１６との慣層向においてその面積
を広い形状にして一膚駕ｋを大きくしてめる＠ ５１３明の効果 以上の夾ｍ例からもわかるように、本発明による十尋体
Ｍ筺では、情脂封止する工４！ｉ！畝２よび所費時間が
短−されるので、屁成果槓−鮎が女愉に１達することが
でき、偏置バリの少なめ外鱗上　　　□のすぐれたもの
となる。Figures 3 and 4 of the case are similar to other methods, in which the surface area of the case IT and the terminal 16 is made wider in the direction of contact between the case IT and the terminal terminal 16, thereby increasing the height of the case IT and the terminal 16. As can be seen from the examples above, the 10 fat M box according to the present invention has an effect of 4! i! Since the ridge 2 and the time required are shortened, the fart result - Ayu can reach 1 female pleasure, resulting in an excellent outer scale □ with fewer eccentric burrs.

４、図ｗＪｏ藺単な１四 ４１図は従来Ｏ混ＩｉＬ集積回路の半導体装置を示す断
面図、第２〜４図は本発明Ｏ混ｇ粂櫨回路の半導体ａｔ
を示す断面図である。4. Figure wJo simple Figure 1441 is a sectional view showing a semiconductor device of a conventional O-mixed IiL integrated circuit, and Figures 2 to 4 are semiconductors of the O-mixed IiL integrated circuit of the present invention.
FIG.

９・・・・・・・・・ケース １０・・・・・・基板載置部 １１・・・・・・−路基板 １２．１４・・・インナー・リード １３・・・・・・端子ターミナル １５・・・・・・シリコン−朧 １６・・・・・・接着剤 （７３１７）代理人　弁理士　　則　近　憲　佑（ほか
１名） 第　ｆ　図 第　３　図 第　２　図 第４　図9... Case 10... Board mounting section 11...- Road board 12.14... Inner lead 13... Terminal terminal 15...Silicon - Oboro 16...Adhesive (7317) Agent Patent Attorney Noriyuki Chika (and 1 other person) Figure f Figure 3 Figure 2 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 上端にターミナルが配設されたケース内に温威＊ａ回路
が形成された基板を畿着剤を介して一定し、咳基板の上
に保ｍｓ′＠層を形成してＩＩ記瓢成集機回路が封止さ
れる半導体装置において、前記保＃Ｉｉ部材層は前記ケ
ースの上潮近傍まで形成されたシリコーン−脂層および
この上に前記ターミナルの上端まで形成された倣Ｍ銅層
とからなることを脣曹とする半導体装置。The board on which the thermal *a circuit is formed is fixed in a case with a terminal arranged on the upper end via a glue, and a protective ms'@ layer is formed on the cough board to complete the process described in Part II. In a semiconductor device in which a mechanical circuit is sealed, the protective #Ii member layer consists of a silicone-resin layer formed up to the vicinity of the top of the case and a copy M copper layer formed thereon up to the upper end of the terminal. Semiconductor devices whose purpose is to become
JP1004582A 1982-01-27 1982-01-27 Semiconductor device Pending JPS58128755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1004582A JPS58128755A (en) 1982-01-27 1982-01-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1004582A JPS58128755A (en) 1982-01-27 1982-01-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58128755A true JPS58128755A (en) 1983-08-01

Family

ID=11739418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1004582A Pending JPS58128755A (en) 1982-01-27 1982-01-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58128755A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4558510A (en) * 1983-03-31 1985-12-17 Tokyo Shibaura Denki Kabushiki Kaisha Method of producing a semiconductor device
WO2022270038A1 (en) * 2021-06-23 2022-12-29 富士電機株式会社 Semiconductor module and method for manufacturing same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4558510A (en) * 1983-03-31 1985-12-17 Tokyo Shibaura Denki Kabushiki Kaisha Method of producing a semiconductor device
WO2022270038A1 (en) * 2021-06-23 2022-12-29 富士電機株式会社 Semiconductor module and method for manufacturing same

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