JPS58128754A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS58128754A
JPS58128754A JP1137182A JP1137182A JPS58128754A JP S58128754 A JPS58128754 A JP S58128754A JP 1137182 A JP1137182 A JP 1137182A JP 1137182 A JP1137182 A JP 1137182A JP S58128754 A JPS58128754 A JP S58128754A
Authority
JP
Japan
Prior art keywords
active element
metal layer
chips
layers
metal layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1137182A
Other languages
Japanese (ja)
Inventor
Masato Murata
村田　真人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1137182A priority Critical patent/JPS58128754A/en
Publication of JPS58128754A publication Critical patent/JPS58128754A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To simplify the inspection of active element chips and to miniaturize the device by a method wherein external leadout electrodes on the rear side of an active element mounting substrate and bonding metal layers belonging in a passive element mounting substrate are bonded fast by means of an electroconductive adhesive. CONSTITUTION:An active element mounting substrate 1 is provided on its surface with active element chip mounting metal layers 2a, 2b, and electrode bonding metal layers 3a-3d separated from said layers 2a, 2b, external leadout electrodes 4a-4d with ends connected to said metal layers 3a-3d and with parts extending to the rear surface. Active element chips 5a, 5b are respectively installed on the layers 2a, 2b. In this condition, with the leadout electrodes 4a-4d respectively led out of the chips 5a, 5b, the chips can be examined independently. Then, bonding metal layers 12a-12d are provided on the surface of a psssive element mounting substrae 11 and conductive wirings 13a, 13b are provided electrically connecting the layers 12a-12d. The electrodes 4a-4d and the layers 12a-12d are respectively bonded with solder 14, which establishes electrical connection for the chips 5a, 5b. The design miniaturizes the device.

Description

【発明の詳細な説明】 本発明は混成集積回路に関する。[Detailed description of the invention] The present invention relates to hybrid integrated circuits.

最近、電子装置の高集積化高機能化が進み、これらの回
路機能を実現する九め、例えば厚膜多層基板による受動
回路素子上に能動素子として例えばＬ８Ｉチップをチッ
プキャリアに封入し、／１ンダ付は等によシ組立てて実
現している。チップキャリアによゐＬ８Ｉチップは回路
規模に応じて複数個に分割される。ｔた、ＴＡＢ（Ｔａ
ｐｅ　ＡｕｔｏｍａｔｅｄＢ・ｎｄｌｎｇ）法と呼ばれ
る方法によりＬＳＩチップを前記多層基板上に搭載した
混成集積回路も製造されている。この様な従来の混成集
積回路は、複数個の能動素子チップを搭載しているため
、組立後の不良能動素子チップの探査が困難であるとい
う欠点がありた。探査の困難性は混成集積回路の回路規
模が大きくなればなる椙大きくなる。ｔた、チップ中ヤ
リア等に１個ずつＬＳＩチップのような能動素子チップ
を封入して厚膜多層基板に搭載する方法はチップキャリ
アケースが大きいため、回踏を小蓋化することに限界が
あるという欠点がありた。Recently, electronic devices have become highly integrated and highly functional, and the ninth step to realizing these circuit functions is to encapsulate, for example, an L8I chip as an active element in a chip carrier on a passive circuit element made of a thick film multilayer substrate. The attachment is achieved by assembling the parts separately. The L8I chip is divided into a plurality of pieces by a chip carrier depending on the circuit scale. Ta, TAB(Ta
A hybrid integrated circuit in which an LSI chip is mounted on the multilayer substrate by a method called pe AutomatedB.ndlng) method is also manufactured. Since such conventional hybrid integrated circuits are equipped with a plurality of active element chips, they have the disadvantage that it is difficult to detect defective active element chips after assembly. The difficulty of exploration increases as the circuit scale of hybrid integrated circuits increases. In addition, the method of enclosing active element chips such as LSI chips one by one in each chip carrier and mounting them on a thick film multilayer substrate requires a large chip carrier case, so there is a limit to making the circuit smaller. There was a drawback.

本発明は上記欠点を除去し、搭載した能動素子チップの
良否の検査が害鳥でしかも小重化が可能な混成集積回路
を提供するものである。The present invention eliminates the above-mentioned drawbacks, and provides a hybrid integrated circuit in which inspection of the quality of mounted active element chips is a nuisance, and which can be made smaller in weight.

本発明の混成集積回路は、絶縁体板の表面に能動素子チ
ップ搭載用金属層と鍍金属層と間隔をおいて設けられる
電極接続用金属層と該電極接続用金属層に一端が接続し
前記絶縁体板を貫通して裏ＷＫ伸びる外部取出し電極と
から成ゐ組を複数組有し、かつ鋏組は互いに絶縁されて
独立である能動素子搭載用基板と、絶縁体板の表面に前
記能動素子搭載用基板裏面の外部取出し電極に対応して
設けられた接続用金属層と誼接続用金属層を電気的に＊
Ｉ１２するように前記絶縁体１［０表面もしくは中を通
って設けられる導体配線を有する受動素子回路基板と、
前記外部取出し電極と前記接続用金属層を接続固着する
導電性接着剤とを虐んで構成される。The hybrid integrated circuit of the present invention includes a metal layer for electrode connection provided on the surface of an insulator plate at a distance from the metal layer for mounting an active element chip and the plated metal layer, and one end connected to the metal layer for electrode connection. It has a plurality of pairs of external lead-out electrodes that extend through the insulator plate and extend from the back WK, and the scissor pairs are mutually insulated and independent active element mounting substrates, and the active element mounting substrates are mounted on the surface of the insulator plate. Electrically connect the connection metal layer and the connection metal layer provided corresponding to the external lead-out electrode on the back side of the element mounting board.
a passive element circuit board having conductor wiring provided on or through the insulator 1[0 as shown in FIG.
It is constructed by pressing a conductive adhesive that connects and fixes the external electrode and the connection metal layer.

本発明の実施例について図面を用いて説明する。Embodiments of the present invention will be described with reference to the drawings.

第１図（１）　、　（ｂ）本発明の一実施例の製造方法
を説明するための工檻順の断面図である。FIGS. 1(1) and 1(b) are cross-sectional views in order of construction for explaining a manufacturing method according to an embodiment of the present invention.

壕ず、Ｉｌ１図偵）Ｋ示すように１能動素子搭載用基板
１は積層した絶縁体板の表面に能動素子チップ搭載用金
属層２Ｍ、２ｂと、これと間隔をおいて設けられる電極
接続用金属層３ａ〜３ｄと、これに一端が接続し裏面に
伸びる外部取出し電極４１〜４ｄを有する。能動素子チ
ップ搭載用金属層２ａ。As shown in Figure 1), the substrate 1 for mounting active elements has metal layers 2M and 2b for mounting active element chips on the surface of the laminated insulator plate, and metal layers 2M and 2b for electrode connection provided at intervals from these layers. It has metal layers 3a to 3d and external lead electrodes 41 to 4d connected at one end to the metal layers and extending to the back surface. Metal layer 2a for mounting active element chips.

２ｂにそれぞれ能動素子チップ５ａｌｌｓｂを搭載し、
金属線６で電極を接続する。セラミック等の絶縁体の蓋
７をガラス半田８で気密封止する。Each of 2b is equipped with an active element chip 5allsb,
Connect the electrodes with a metal wire 6. A lid 7 made of an insulator such as ceramic is hermetically sealed with glass solder 8.

この状態では能動素子チップ５ａ　Ｉ　５ｂはそれぞれ
外部取出し電極４８〜４ｄが独立して引出されているか
ら単独に検査できる。従って不要チップの検出は容易で
ある。In this state, the active element chips 5a, I, and 5b can be inspected individually because the external lead-out electrodes 48 to 4d are drawn out independently. Therefore, it is easy to detect unnecessary chips.

次に、第１図（ｂ）Ｋ示すように、受動素子搭載用基板
１１は絶縁体で作られ、その表面Ｋａ動素子搭載用基板
裏面の外部取出し電極４ａ〜４ｄＫ対応して接続用金属
層１２１１〜１２ｄを有し、ｔた絶縁体の中を通るかも
しくは絶縁体の表面の他の部分を通って接続用金属層１
２１〜１２ｄを電気的に結ぶ導体配線１３ａ、１３ｂを
有す。外部取出し電極４ａ〜４ｄと接続用金属１２８〜
１２ｄとをそれぞれ半田１４で接着することＫより能動
素子チップ５１１５ｂは電気的に接続し回路を構成する
。このような構造にすると従来のチップキャリア型のＬ
ＳＩより小型化できる。また能動素子チップの変更も容
易である。Next, as shown in FIG. 1(b)K, the passive element mounting board 11 is made of an insulator, and a connection metal layer is formed corresponding to the external lead-out electrodes 4a to 4dK on the back surface of the passive element mounting board 11. 1211 to 12d, and the connecting metal layer 1 passes through the t-shaped insulator or through other parts of the surface of the insulator.
It has conductor wiring 13a, 13b that electrically connects 21 to 12d. External extraction electrodes 4a to 4d and connection metal 128 to
By bonding the active element chips 5115b and 12d with solder 14, the active element chips 5115b are electrically connected to form a circuit. With this structure, the conventional chip carrier type L
Can be made smaller than SI. Furthermore, it is easy to change the active element chip.

第２図は本発明の他の実施例の能動素子搭載用基板の断
面図である。FIG. 2 is a sectional view of an active element mounting substrate according to another embodiment of the present invention.

この実施例では基板２１に非積層のものを用い、また能
動素子チップ５ｍ、５ｂの保傾にはシリコン樹脂２２を
用いている。基板１．２１は剛体でなくても曳く、７レ
キシプルプリント基板等でも喪い。In this embodiment, a non-laminated substrate 21 is used, and a silicone resin 22 is used to hold the active element chips 5m and 5b. The board 1.21 can be used even if it is not a rigid body, and it can be used even if it is a 7 lexiple printed circuit board.

上記実施例では一つの受動素子搭載用基板１１に能動素
子搭載用基板ｌを１個だけ載せであるが、受動素子搭載
用基板１１を大きくして複数個の能動素子搭載用基板を
載せることも可能である。In the above embodiment, only one active element mounting board l is mounted on one passive element mounting board 11, but the passive element mounting board 11 may be enlarged to mount a plurality of active element mounting boards. It is possible.

以上詳細に説明したように１本発明によれば、能動素子
チップの良否検査を容易に実現でき、しかも小型化が容
易な混成集積回路が得られるのでその効果は大きい。As described in detail above, according to the present invention, it is possible to easily test the quality of active element chips, and furthermore, it is possible to obtain a hybrid integrated circuit that can be easily miniaturized, which is highly effective.

【図面の簡単な説明】[Brief explanation of the drawing]

ｍ１図（ａ）　、　（ｂｌは本発明の一実施例の製造方
法を説明するための工程項の断面図、第２図は本発明の
他の実施例の能動素子搭載用基板の断面図である。 １・・・・・・能動素子搭載用基板、２ｍ、　２ｂ・・
・・・・能動素子チップ搭載用金属層、３ａγ３ｄ・・
・・・・電極接続用金属層、４息〜４ｄ・・・・・・外
部取出し電極、５ｍ＋５ｂ・・・・・・能動素子チップ
、６・・・・・・金属線、７・・・・・・蓋、８・・・
・・・半田、１１・・・・・・受動素子搭載用基板、１
２１〜１２ｄ・・・・・・接続用金属層、１３ａ、１３
ｂ・・・・・・導体配線、１４・・・・・・半田、２１
・・・・・・能動素子搭載用基板、２２・・・・・・シ
リコン樹脂。Figure m1 (a), (bl is a cross-sectional view of the process section for explaining the manufacturing method of one embodiment of the present invention, and Figure 2 is a cross-sectional view of a substrate for mounting an active element according to another embodiment of the present invention. Yes. 1...Substrate for mounting active elements, 2m, 2b...
...Metal layer for mounting active element chip, 3aγ3d...
...Metal layer for electrode connection, 4 breaths to 4d...External extraction electrode, 5m+5b...Active element chip, 6...Metal wire, 7... ...Lid, 8...
...Solder, 11...Passive element mounting board, 1
21-12d... Connection metal layer, 13a, 13
b... Conductor wiring, 14... Solder, 21
...Substrate for mounting active elements, 22...Silicon resin.

Claims (1)

【特許請求の範囲】[Claims] 絶縁体板の表ＷＫ能動素子チップ搭噴用金属層と腋金属
層と間隔をおいて設けられる電ｉｉ＊続用金属層と鋏電
極接続用金属層に一端が接続し前記絶縁体板を貫通して
裏ＷｔＣ伸びる外部取出し電極とから成る組を複数組有
し、かつ咳組は互いに絶縁されて独立である能動素子搭
載用基板と、絶縁体板の表面に前記能動素子搭載用基板
裏面の外部取出し電極に対応して設けられた接続用金属
層と誼接続用金属層を電気的に接続するように前記絶縁
体板の表面もしくは中を通って設けられる導体配線を有
する受動素子回路基板と、前記外部亀山し電極と前記接
続用金属層を接続固着する導電性接着剤とを含むことを
待機とする混成集積回路。One end of the insulator plate connects to the electric connection metal layer and the scissor electrode connection metal layer, which are provided at intervals from the front WK active element chip mounting metal layer and the armpit metal layer, and penetrates the insulator plate. A substrate for mounting an active element, which has a plurality of sets consisting of externally taken-out electrodes extending from the back WtC, each of which is insulated and independent from each other, and a back surface of the substrate for mounting the active element on the surface of the insulator plate. A passive element circuit board having a conductive wiring provided on or through the insulator plate to electrically connect a connecting metal layer provided corresponding to an externally taken-out electrode and a connecting metal layer. , a hybrid integrated circuit comprising: a conductive adhesive for connecting and fixing the external helmet electrode and the connecting metal layer;
JP1137182A 1982-01-27 1982-01-27 Hybrid integrated circuit Pending JPS58128754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1137182A JPS58128754A (en) 1982-01-27 1982-01-27 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1137182A JPS58128754A (en) 1982-01-27 1982-01-27 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS58128754A true JPS58128754A (en) 1983-08-01

Family

ID=11776150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1137182A Pending JPS58128754A (en) 1982-01-27 1982-01-27 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS58128754A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02288252A (en) * 1989-04-27 1990-11-28 Nec Corp Semiconductor device
WO1991005370A1 (en) * 1989-09-27 1991-04-18 Gec-Marconi Electronic Systems Corp. Hybrid module electronics package
USRE34291E (en) * 1989-09-27 1993-06-22 Gec-Marconi Electronic Systems Corp. Hybrid module electronics package
US5237204A (en) * 1984-05-25 1993-08-17 Compagnie D'informatique Militaire Spatiale Et Aeronautique Electric potential distribution device and an electronic component case incorporating such a device
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
JPH08316407A (en) * 1995-05-15 1996-11-29 Nec Corp Manufacture of composite semiconductor package
US5811868A (en) * 1996-12-20 1998-09-22 International Business Machines Corp. Integrated high-performance decoupling capacitor

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237204A (en) * 1984-05-25 1993-08-17 Compagnie D'informatique Militaire Spatiale Et Aeronautique Electric potential distribution device and an electronic component case incorporating such a device
JPH02288252A (en) * 1989-04-27 1990-11-28 Nec Corp Semiconductor device
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