JPS58122736A - Formation of insulating film - Google Patents
Formation of insulating filmInfo
- Publication number
- JPS58122736A JPS58122736A JP333482A JP333482A JPS58122736A JP S58122736 A JPS58122736 A JP S58122736A JP 333482 A JP333482 A JP 333482A JP 333482 A JP333482 A JP 333482A JP S58122736 A JPS58122736 A JP S58122736A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- plasma
- electrode
- insulating film
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
Landscapes
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
Abstract
Description
【発明の詳細な説明】
本発明１１半導体電子装皺製作における絶縁膜形成法に
関するものであるＯ
ｗＪ１図は従来の絶縁膜形成法における電極と基板との
関係を示すもので、図において、１は電極、２は基板、
３に電極を示すものであり、電極と基板は電気的に接触
してセ９．かかる状態に１プラズマを生成させ、これに
よって絶縁膜を形成していた。この構造において電極１
．３閣に高周波電カケ加え、プラズマ金発生させた時の
Ａ−Ｂ方向のｆＬ流電位分布ｔ％第２図１Ｃ示す０図に
示すように、１１Ｅ憔１上に設置した基板にフ゛ラズマ
に対し。DETAILED DESCRIPTION OF THE INVENTION This invention 11 relates to an insulating film forming method in the manufacture of semiconductor electronic devices. is the electrode, 2 is the substrate,
3 shows the electrode, and the electrode and the substrate are in electrical contact and 9. In this state, plasma was generated to form an insulating film. In this structure, electrode 1
．． When a high-frequency electric chip is added to the three cabinets and plasma gold is generated, the fL current potential distribution t% in the A-B direction is shown in Figure 2. .
負の電位ｔ＋し、このため化イオンが基板に衝突し、損
傷を与える。−例としてＧａ Ａｓ電界効米ト２ンジス
タの電極を苓する主１１１１ｍにシリコン電化ａｔ形成
した時の膜形成前後のトレイン電ｆｉｒ第３−に示す。The potential t+ is negative, so that ions collide with the substrate and cause damage. - As an example, the train voltage before and after film formation when silicon electrification is formed on the main 1111m electrode of a GaAs field effect transistor is shown in Figure 3.
実線Ｃは膜形成前のドレイン電流、破線りは膜形成後の
ドレイン電流である。第３図より明らかなように従来法
ｅこおいては、膜形ａｒＣよりドレイン電流が着しく減
少し＆素子特性が劣化してしまうという欠点を鳴してい
た。本発明に上記の欠点を抜書するために提案されたも
のである。The solid line C is the drain current before film formation, and the broken line C is the drain current after film formation. As is clear from FIG. 3, the conventional method e has the disadvantage that the drain current is significantly reduced and the device characteristics are deteriorated compared to the film type arC. This invention has been proposed to overcome the above-mentioned drawbacks.
本発明は、半導体上の絶縁膜形成時、半導体と電極と會
電気的に絶縁することｋｑ＃黴とし、その目的は、絶縁
膜形故に伴う半導体損ＩＩを防止することにある。In the present invention, when forming an insulating film on a semiconductor, the semiconductor is electrically insulated from an electrode, and the purpose thereof is to prevent semiconductor loss II due to the shape of the insulating film.
前記の目的に達成するため、本発明はプラズマ−ＣＶＤ
法にニジ、半導体基板上に絶−膜上形成する場合におい
て、電極と牛４体基板を電気的ＶＣ絶縁し、かつ該半専
体基板ｔプラズマ中に保持することにより、絶縁ａｋ膜
形成ることｔ−ｗｅとする絶縁−形成法を発明の費旨と
するものである。To achieve the above object, the present invention utilizes plasma-CVD
When forming an insulating film on a semiconductor substrate according to the method, an insulating AK film can be formed by electrically insulating the electrode and the substrate with VC and holding the semi-dedicated substrate in t plasma. The subject matter of the invention is an insulation forming method called t-we.
次に不発明の実施例全添附図面について説明する０なお
実施例は一つの例示でおって、本発明の精神を逸脱しな
ｉ範囲内で、徳々の変更あるいは改良を行いうろことは
云うまでもない。Next, we will explain all the attached drawings of non-inventive embodiments.It should be noted that the embodiments are merely illustrative, and that moral changes or improvements may be made within the scope of the invention without departing from the spirit of the invention. Not even.
第４図は本発明の絶ｉｔｓ形成法の実施例を示すもので
あり、図において、ｌは電極、２は半導体基板、３は電
極、４は絶縁物である。本発明は、９４図に示す如く、
電ｍｌ上ｒｃ例えば、石英のような絶縁物４を麹き、こ
の絶縁物上に半導体基板を設置し、しかる後プラズーｔ
ｆ発生させて絶縁膜を形成せんとするものである。FIG. 4 shows an embodiment of the insulator forming method of the present invention, and in the figure, l is an electrode, 2 is a semiconductor substrate, 3 is an electrode, and 4 is an insulator. The present invention, as shown in Figure 94,
For example, an insulating material 4 such as quartz is molded, a semiconductor substrate is placed on this insulating material, and then a plasma t
The purpose is to form an insulating film by generating f.
第５図は電極１．３間に高周波を加え、プラズマを生成
した場合のＡＢ方向の電位を示したものであり、電極付
近で電位か低くなった部分（１！１＆廃）ｓ）かできる
０不発明において灯半導体基板１に陰極陣１部でなく、
絶縁物を介して、プラズマ中に設置するため、半導体基
板がイオンに対して持つ電位は無視できるほどでろＶ、
従ってイオン第６図は本発明に↓り％例えばＧａＡｓ電
界効米トランジスタの電極を有する主面−にシリコン窒
化ａｔ形成した時の膜形成前後のドレイン電ｇｔ−示し
良ものである。実線Ｃ框膜形成前のドレイン電Ｒ１破１
１ｉ１Ｄは換形欣後のドレイン１１流を示す。Figure 5 shows the potential in the AB direction when high frequency is applied between electrodes 1 and 3 to generate plasma, and a portion (1! 1 & waste) s) where the potential is low near the electrodes is formed. In the invention, there is not only one part of the cathode layer on the lamp semiconductor substrate 1,
Since the semiconductor substrate is placed in plasma through an insulator, the potential that the semiconductor substrate has with respect to ions is negligible.
Therefore, FIG. 6 shows the drain voltage gt before and after film formation when silicon nitride is formed on the main surface having electrodes of, for example, a GaAs field effect transistor according to the present invention. Solid line C Drain voltage R1 break 1 before frame film formation
1i1D indicates the drain 11 flow after conversion.
絶縁膜形成によるドレイン電流の減少はなく、イオン衝
撃による損傷は鉋められない。There is no decrease in drain current due to the formation of the insulating film, and no damage caused by ion bombardment is observed.
以上説明したように、本発明に↓れｄ半導体基板上にプ
ラズマＣＶＤ法にエフ絶縁ｌｌＩ″ｆ：形成する場合に
おいて、半導体基板と電極とを電気的に絶縁し、かつ該
半導体基板上プラズマ中に保持することにぶり、骸半導
体基板へのイオン債撃會小ならしめることができ、よっ
て半導体基板の損傷を伴わずに、絶縁＠形成を行なうこ
とができる効果１有する０As explained above, in accordance with the present invention, in the case of forming an F insulator on a semiconductor substrate by plasma CVD method, the semiconductor substrate and the electrode are electrically insulated, and the semiconductor substrate is exposed to the plasma on the semiconductor substrate. By holding the semiconductor substrate at a low temperature, the ion bombardment on the semiconductor substrate can be minimized, and therefore insulation can be formed without damaging the semiconductor substrate.
＃Ｉｌ−は従来法によるプラズマ−〇ＶＤ杷縁験形成装
置の電極部の断面図、第２図に従来法によるプラズマ−
ＣＶＤ４１９縁膜形成装置の電極間の直流電位分布を示
す０第３図は従来法による膜形成前後のドレイン電流を
示す。１ｇ４図は本発明のプラズマ−〇ＶＤ装置の電極
部の断面図、第ｓｍ社本発明のプラズマ−ｃｖＤｔｃ＆
の電極間の電位分布、＠６図は本発明による膜形成前後
のドレイン電Ｒｔ示す。
ｌ・・・・・・電極、２・・・・・・半導体基板、３・
・・・・・電極、４・・・・・・絶縁物
特許出願人 日本電信電話公社#Il- is a cross-sectional view of the electrode part of the conventional plasma method.
FIG. 3, which shows the DC potential distribution between the electrodes of the CVD419 edge film forming apparatus, shows the drain current before and after film formation by the conventional method. Figure 1g4 is a sectional view of the electrode part of the plasma-〇VD device of the present invention, and the plasma-cvDtc &
Figure 6 shows the drain voltage Rt before and after film formation according to the present invention. l... Electrode, 2... Semiconductor substrate, 3.
... Electrode, 4 ... Insulator patent applicant Nippon Telegraph and Telephone Public Corporation
Claims (1)
ｔ形成する場合において、電極と半導体基板を電気的に
絶縁し、かつ該半導体基板をプラズマ中に保持すること
りｃより、絶縁ａｔ膜形成ること１ｒ特徴とする絶縁膜
形成法。Insulating YIl is deposited on a semiconductor substrate by plasma-CVD method.
An insulating film forming method characterized in that, in the case of forming an insulating film, an insulating AT film is formed by electrically insulating an electrode and a semiconductor substrate and holding the semiconductor substrate in plasma.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP333482A JPS58122736A (en) | 1982-01-14 | 1982-01-14 | Formation of insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP333482A JPS58122736A (en) | 1982-01-14 | 1982-01-14 | Formation of insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58122736A true JPS58122736A (en) | 1983-07-21 |
Family
ID=11554449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP333482A Pending JPS58122736A (en) | 1982-01-14 | 1982-01-14 | Formation of insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58122736A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4616597A (en) * | 1984-10-31 | 1986-10-14 | Rca Corporation | Apparatus for making a plasma coating |
| JPH0394064A (en) * | 1989-09-07 | 1991-04-18 | Mitsubishi Heavy Ind Ltd | Method and apparatus for producing silicon nitride film |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5190500A (en) * | 1975-02-05 | 1976-08-07 | ||
| JPS5368171A (en) * | 1976-11-30 | 1978-06-17 | Hitachi Ltd | Method and apparatus for plasma treatment |
| JPS545636A (en) * | 1977-06-15 | 1979-01-17 | Sanyo Electric Co Ltd | Input/output control system for electronic computer |
| JPS5433668A (en) * | 1977-08-22 | 1979-03-12 | Hitachi Ltd | Plasma deposition unit |
| JPS5633839A (en) * | 1979-08-29 | 1981-04-04 | Hitachi Ltd | Plasma treatment and device therefor |
-
1982
- 1982-01-14 JP JP333482A patent/JPS58122736A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5190500A (en) * | 1975-02-05 | 1976-08-07 | ||
| JPS5368171A (en) * | 1976-11-30 | 1978-06-17 | Hitachi Ltd | Method and apparatus for plasma treatment |
| JPS545636A (en) * | 1977-06-15 | 1979-01-17 | Sanyo Electric Co Ltd | Input/output control system for electronic computer |
| JPS5433668A (en) * | 1977-08-22 | 1979-03-12 | Hitachi Ltd | Plasma deposition unit |
| JPS5633839A (en) * | 1979-08-29 | 1981-04-04 | Hitachi Ltd | Plasma treatment and device therefor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4616597A (en) * | 1984-10-31 | 1986-10-14 | Rca Corporation | Apparatus for making a plasma coating |
| JPH0394064A (en) * | 1989-09-07 | 1991-04-18 | Mitsubishi Heavy Ind Ltd | Method and apparatus for producing silicon nitride film |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5581146A (en) | Micropoint cathode electron source with a focusing electrode | |
| US3419761A (en) | Method for depositing silicon nitride insulating films and electric devices incorporating such films | |
| US3556966A (en) | Plasma anodizing aluminium coatings on a semiconductor | |
| JP2002076358A (en) | Short channel switching element and its manufacturing method | |
| JPS58122736A (en) | Formation of insulating film | |
| JPH104085A (en) | Dry etching and apparatus therefor | |
| JP3578739B2 (en) | Plasma equipment | |
| JP2000036486A (en) | Plasma processing device and method therefor | |
| JP2851766B2 (en) | Electrostatic chuck | |
| TW460982B (en) | Bipolar transistor with passivation layer scheme and method of making the same | |
| JP4723797B2 (en) | CMOS transistor | |
| JPS60133757A (en) | Manufacture of thin film transistor | |
| JPS61264174A (en) | Dc bias sputtering method | |
| JP2001291869A (en) | Semiconductor device and method for manufacturing the same | |
| JPH04186863A (en) | Electrostatic attracting equipment | |
| TW202307907A (en) | Plasma treatment apparatus, lower electrode assembly and forming method thereof | |
| JPH11219852A (en) | Electret device | |
| JPS63102319A (en) | High frequency electrode | |
| US6171912B1 (en) | Method of manufacturing a semiconductor device comprising a field effect transistor | |
| JP2004023040A (en) | Manufacturing method of semiconductor device | |
| JP3071450B2 (en) | Microwave plasma processing equipment | |
| JPH10209126A (en) | Plasma etching equipment | |
| JPH07207471A (en) | Plasma etching device | |
| KR100268944B1 (en) | Method of fabrication semiconductor device | |
| TW202121579A (en) | Wafer retaining device and plasma processing equipment characterized by improving the reliability of retaining a wafer |