JPS58122226U - tape recorder circuit - Google Patents
tape recorder circuitInfo
- Publication number
- JPS58122226U JPS58122226U JP1655582U JP1655582U JPS58122226U JP S58122226 U JPS58122226 U JP S58122226U JP 1655582 U JP1655582 U JP 1655582U JP 1655582 U JP1655582 U JP 1655582U JP S58122226 U JPS58122226 U JP S58122226U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- governor
- switch
- tape recorder
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の回路構成図、第2図は本考案の回路構成
図である。
2・・・増幅!路、4・・・モータ、5・・・ガバナー
回路、6・・・ミューティング用トランジスタ、7・・
・ミューティング端子、8・・・ガバナ一端子、9・・
・スイッチ、12・・・スイッチング回路、13,14
・・・バイアス′ 抵抗。FIG. 1 is a conventional circuit configuration diagram, and FIG. 2 is a circuit diagram of the present invention. 2...Amplify! 4... Motor, 5... Governor circuit, 6... Muting transistor, 7...
・Muting terminal, 8... Governor terminal, 9...
・Switch, 12...Switching circuit, 13, 14
...Bias′ resistance.
Claims (1)
−回路のガバナ一端子を早送り(又は巻戻し)時に閉成
される単一のスイッチ及び該スイッチの閉成により反転
状態となるスイッチング回路を介してアースし、増幅回
路をミューティング動作させる滅同時にガバナー回路を
不動作にするように構成し、前記スイッチの開放時に電
源電圧が降下し゛ ても前記ミューティング端子にかか
る電圧を多ニー −ティング動作電圧以上に保持する
ようにスイッチング回路のバイアス抵抗を設定したこと
を特徴とするテープレコーダー回路。
2゜Amplifier circuit muting terminal and motor governor,
- The governor terminal of the circuit is grounded through a single switch that is closed during fast forwarding (or rewinding) and a switching circuit that is inverted when the switch is closed, and the amplifier circuit is muted at the same time. The governor circuit is configured to be inoperative, and the bias resistor of the switching circuit is configured so that the voltage applied to the muting terminal is maintained at a voltage higher than the multi-neating operating voltage even if the power supply voltage drops when the switch is opened. A tape recorder circuit characterized by the following settings.
2゜
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1655582U JPS58122226U (en) | 1982-02-08 | 1982-02-08 | tape recorder circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1655582U JPS58122226U (en) | 1982-02-08 | 1982-02-08 | tape recorder circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58122226U true JPS58122226U (en) | 1983-08-19 |
Family
ID=30028917
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1655582U Pending JPS58122226U (en) | 1982-02-08 | 1982-02-08 | tape recorder circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58122226U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS528469A (en) * | 1975-07-09 | 1977-01-22 | Nippon Electric Co | Automatic soldering device |
-
1982
- 1982-02-08 JP JP1655582U patent/JPS58122226U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS528469A (en) * | 1975-07-09 | 1977-01-22 | Nippon Electric Co | Automatic soldering device |
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