JPS58116880A - Image pickup device - Google Patents
Image pickup deviceInfo
- Publication number
- JPS58116880A JPS58116880A JP56215342A JP21534281A JPS58116880A JP S58116880 A JPS58116880 A JP S58116880A JP 56215342 A JP56215342 A JP 56215342A JP 21534281 A JP21534281 A JP 21534281A JP S58116880 A JPS58116880 A JP S58116880A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- image pickup
- signal
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/0035—User-machine interface; Control console
- H04N1/00405—Output means
- H04N1/00408—Display of information to the user, e.g. menus
- H04N1/0044—Display of information to the user, e.g. menus for image preview or review, e.g. to help the user position a sheet
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/21—Intermediate information storage
- H04N1/2104—Intermediate information storage for one or a few pictures
- H04N1/2112—Intermediate information storage for one or a few pictures using still video cameras
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/21—Intermediate information storage
- H04N1/2104—Intermediate information storage for one or a few pictures
- H04N1/2112—Intermediate information storage for one or a few pictures using still video cameras
- H04N1/212—Motion video recording combined with still video recording
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
- H04N5/772—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera the recording apparatus and the television camera being placed in the same enclosure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N2101/00—Still video cameras
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
本発明紘連続撮像とワンシ冒ットの撮像との切換が容易
に可能な撮像装置に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an imaging apparatus that can easily switch between wide continuous imaging and single shot imaging.
従来ビデオカメラにおいて社連続撮像のみが可能であＩ
り１ ワンシ曹ットだけの撮像は不可能であった。本発
明はこの様な問題を解決し得る新規な改善された撮像装
置を提供する事を目的としている・
その為に本発明で社連続毫−ドからワンシｌット撮像又
社スチルモード撮偉へ切換える際、スイッチ手段の操作
によ多、それ迄の走査周期と全く別の新たな蓄積及び走
査を行なう為同期信゛号発生手段を切換える様にしてい
る。Conventional video cameras are only capable of continuous imaging;
ri1 It was impossible to image only the swanfish. It is an object of the present invention to provide a new and improved imaging device capable of solving such problems. To this end, the present invention provides a new and improved imaging device capable of solving these problems. When switching to the synchronous signal generating means, the synchronizing signal generating means is changed by operating the switch means in order to perform new accumulation and scanning completely different from the previous scanning period.
叉、このスチルモードの間だけ露出パテメータード中に
撮像手段からの映像出力を一時記憶する記憶手段を設け
、この記憶を周期的にリセットすると共に、スチルセー
ドに切換える事によ夕このリセットを中止し、かつ、前
記記憶手段の内宮を篭エタ一手段に導びく様為している
ので連続モード中にスチルモードが短時聞入ってもモニ
タに乱れが生じない。Further, a storage means is provided to temporarily store the image output from the imaging means during exposure parameter metering only during this still mode, and this memory is reset periodically, and this reset is canceled in the evening by switching to still mode, In addition, since the inner memory of the storage means is guided to the storage means, even if the still mode enters the continuous mode for a short time, the monitor will not be disturbed.
又、本発明で社、連続モード中撮像手段の出力の一部を
周期的にサンプルホールドする手段を有し、この出力を
被写体輝度情報として利用すると、共にスチルモードへ
の切換えに伴ってこのサンプリンｌを停止する事によ多
連続モード中の情報をそのまま利用できる橡にした点に
ある。In addition, the present invention has a means for periodically sampling and holding a part of the output of the imaging means during continuous mode, and when this output is used as subject brightness information, this sample and hold is also provided when switching to still mode. By stopping 1, the information in the multiple continuous mode can be used as is.
又、スチル毫−ドの少なくとも電荷転送期間中は撮儂素
子への光入射を禁止する様シャッタを設けているのでス
ミア発生が抑えられる等の特徴を有するものである。Further, since a shutter is provided to prevent light from entering the image pickup element at least during the charge transfer period of the still screen, it is possible to suppress the occurrence of smear.
以下図面に基づき本発明の詳細な説明する。The present invention will be described in detail below based on the drawings.
第１図は本発明の撮嘗装置の構成の一例を示すブーツタ
図、第２囚社同ブロック図の１！郁タイミンｌを示す図
、第５図は第１図示モードセレクタ及び連続モード指示
回路等の論理図、第４図は撮儂素子の構成模式図である
。FIG. 1 is a boot diagram showing an example of the configuration of the imaging device of the present invention, and 1 of the block diagram of the second prisoner company. FIG. 5 is a logic diagram of the mode selector and continuous mode instruction circuit shown in the first diagram, and FIG. 4 is a schematic diagram of the configuration of the image pickup element.
図中Ｌ８は撮儂党学系、ムＰ轄絞１ ａＨＴ社セス回路
、ＭＴｘ＃ｉ該プロセス回路からの真赤）、Ｇ（Ｊｉ）
、Ｂ（實）出力を色差信号（凡−Ｙ）、（Ｂ−Ｙ）及び
輝度信号Ｙに変換する！トリオ１回路、Ｐ８２＃ｉｌｌ
ｅｍ用信号処理回路、′＆Ｈ紘記鍮ヘッド、嶌ｑＰＧ＃
ｉ該ヘッドを１トラツクずつシフトする為の夫々フック
ギア及びピニオンギアである。In the figure, L8 is taken by the photographer, MU P control 1 aHT company process circuit, MTx#i bright red from the process circuit), G (Ji)
, B (actual) output to color difference signal (B-Y), (B-Y) and luminance signal Y! Trio 1 circuit, P82#ill
Signal processing circuit for em, '&H Hiroki brass head, ShimaqPG#
i A hook gear and a pinion gear, respectively, for shifting the head one track at a time.
Ｍ２社ビニオンギアＰＧを駆動する為のパルスモー！、
ａＭＣは該パルスモー！Ｍ２を後述のジ−タンス制御回
路８ＣＴＬからの、例えば垂直同期信号により同期制御
するシフト制御回路である。Pulse motor for driving M2 company's Binion Gear PG! ,
aMC is the pulse mo! This is a shift control circuit that synchronously controls M2 using, for example, a vertical synchronization signal from a jitance control circuit 8CTL, which will be described later.
Ｄは例えば磁気ディスタの如き記録媒体であって該ディ
スクはモータＭ１によ１回転される。ａＭＣは該毫−タ
の回転を制御するディスクモータ制御回路である。尚！
トリクス回路ＭＴｘの出力はスイッチｓ、ｗ４を介して
彎二ター装置に警続■能である。Ｄ凰１社前記撮健素子
ＩＤの蓄積、転送、読み出し等の駆動パルスを生成する
ドライバ回路であ多、同期信号発生回路８ＹＮＣ又はシ
ーヶ／ス制御回路８ＣＴｌ、の出力により同期制御され
る。Ｃａは基準信号発生器である。１Ｇは前記！トリク
ス回路ＭＴＸの出力からＹ信号を抜き出して積分する積
分回路で、＆はそのリセット端子である。このリセット
端子ＲＫａ前記同期信号発生器８ＹＮＣの第２園示の如
き出力の立下りによ）パルスを形成するワンシ冒ット回
路０８１の出力端が接続されている。D is a recording medium such as a magnetic disk, and the disk is rotated once by a motor M1. aMC is a disk motor control circuit that controls the rotation of the motor. still!
The output of the trix circuit MTx can be connected to the converter unit via switches s and w4. This driver circuit generates drive pulses for storage, transfer, readout, etc. of the sensor ID, and is synchronously controlled by the output of the synchronization signal generation circuit 8YNC or the sequence control circuit 8CTl. Ca is a reference signal generator. 1G is mentioned above! This is an integrating circuit that extracts and integrates the Y signal from the output of the trix circuit MTX, and & is its reset terminal. This reset terminal RKa is connected to the output end of a one-shot circuit 081 which forms a pulse (by the fall of the output of the synchronizing signal generator 8YNC as shown in the second diagram).
ＩＨＣｆｉ本発明に係るサンプルホールド回路でありて
前記積分−路の出力を所定のタイミングでサンプルし、
次のすンプル時点迄ネールドする。８紘そのサンプル信
号入力端で前記同期信号発生器出力の立上〉でパルスを
形成するワンシ曹ット回ｇｏｓ２の出力がアンドゲート
ＡＮＤを介して入力されている。IHCfi is a sample and hold circuit according to the present invention, which samples the output of the integration path at a predetermined timing,
Nailed until the next sample. 8. At its sample signal input terminal, the output of the output clock GOS2, which forms a pulse at the rising edge of the synchronizing signal generator output, is inputted via an AND gate.
サンプルホールド回路８ＨＣの出力は演算回路ＯＰＫ入
力され、予め入力された蓄積時間設定回１Ｉ８１ｉ１の
出力又社固定の蓄積時間指示回路８′Ｂ２、又轄紋多値
設定回路−Ｅ５の出力と共に演算され、その出カム又Ｆ
ｉＢに第３図に示される如くコントー−ル人力ａ−ｃ
＃）状態に応じて選択的に出力される。The output of the sample and hold circuit 8HC is inputted to the calculation circuit OPK, and is calculated together with the output of the accumulation time setting circuit 1I81i1 input in advance, the fixed accumulation time instruction circuit 8'B2, and the output of the multi-value setting circuit E5. , its output cam again F
iB is controlled by human power a-c as shown in Figure 3.
#) Selectively output according to the state.
尚１コントロール入力端１〜Ｃにはゲート回路電又はＧ
５を介して夫々モードセレクタＭ８の出力、連続モード
指示回路ＣＤが接続されている。又ゲ−）０４ 、Ｇ５
ｔｉＲ８フリップ７ａッグＦＦｏＱ出力により制御され
、該Ｑ出力がハイレベルの時Ｇ４が開き、Ｇ５が閉じる
。又Ｑ出力がｖｓ％レベルの時祉この逆となる。Furthermore, gate circuit voltage or G is connected to 1 control input terminals 1 to C.
The output of the mode selector M8 and the continuous mode instruction circuit CD are connected through the respective terminals 5 and 5. Mataga-)04, G5
It is controlled by the tiR8 flip 7a and FFoQ output, and when the Q output is at a high level, G4 opens and G5 closes. Also, when the Q output is at the vs% level, the opposite is true.
演算回路ＯＰのム出力に社駆動回路ＤＲ２を介して電流
計ムＭのコイルが接続されており、ム出力のレベルに応
じて電流針ムＭへの通電量が変化する。又電電流計の可
動部は前記絞◆ＡＰの絞多量を変化させる様構成されて
いる。A coil of an ammeter M is connected to the output of the arithmetic circuit OP via a drive circuit DR2, and the amount of current applied to the current needle M changes depending on the level of the output. Further, the movable part of the ammeter is configured to change the amount of aperture of the aperture ◆AP.
演算回路ＯＰのＢ出力端ｄ Ａ／Ｄコンバータｊにを介
してプリセッタプルカウンタＣＮｉのグリセット入力端
Ｐｒ・に接続されてお９、蚊カクｌりのクロック人力Ｃ
ＬＫは前記基準発振器の出力が入力される。ｃ’ｑプリ
セット値迄タロツタをカウントした時１パルスを発生す
る出力端、Ｒはりセット入力端であシ、該リセット端Ｒ
は前記フックプ７−ツプＦＦｏＱ出力に接続されている
。又出力端Ｃは所定のパルス巾（第２独中Ｔｓ ）を有
する立上伽同期のワンシ画ット回路０８５を介してシャ
ッター駆動回路ＤＲ３に入力され、このワンシ曹ット１
路の出力がハイレベルの間だけシャッタを閉成させる様
マｌネットＭｇＫ通電を行なう。尚、本ＩＩ＠に係るシ
ャッタ社従来の銀塩フィルム用シャッタとは異なり、撮
像素子の受光部から蓄積部への転送期間やに前記受光部
への光入射を阻止する為の−のであり、通常は開成する
方向に付勢等されてお今、前記マグネットへ通電されて
いる間だけ撮像素子へり光入射を鐘断する。The B output terminal d of the arithmetic circuit OP is connected to the reset input terminal Pr of the presetter pull counter CNi via the A/D converter j.
The output of the reference oscillator is input to LK. c'q Output terminal that generates one pulse when counting tarots up to preset value, R beam set input terminal, and reset terminal R
is connected to the hook FFoQ output. Further, the output terminal C is inputted to the shutter drive circuit DR3 via a one-shot circuit 085 synchronized with the start-up signal having a predetermined pulse width (second Ts).
Marnet MgK is energized so that the shutter is closed only while the output of the circuit is at a high level. Note that, unlike Shutter's conventional silver halide film shutter according to Book II@, this shutter is used to prevent light from entering the light receiving section during the transfer period from the light receiving section of the image sensor to the storage section. Normally, it is biased in the direction of opening and cuts off light incident on the image sensor only while the magnet is energized.
崗、前記ワンシ曹ット回路０８３の出力は立下多同期の
ワンシ曹ット回路を介しぞ前記ツリツブフロッグＦＦの
リセット端に入力している。ＧＨは本ＩＡ＠に係る記―
再生ヘッドで、鋏ヘッドは前記フリツプフーツ１Ｆｒ＃
）Ｑｌ力がローレベルの間、磁気ディスタＤの所定カド
ラックに対して記録用信号部１１ＨＩＩＰ８２の映像出
力をスイッチ８Ｗ５を介して記鍮する事ができると共に
、前記フリップ７ａツグのＱ出力がハイレベルとなると
・側に切換わる事によ夕記鍮された映像信号を再生信号
ｌ＆環回路Ｐ８５ｉ（導き、スイッチ８Ｗ４を介してこ
れをモニター装置ＭＴＶＫよ！モニターし得る機構成さ
れている。尚１スイツチ８Ｗ５〜８Ｗ５は前記）替ツブ
フロップＦＦＦ）Ｑ出力がハイレベルの時ｅ側、ローレ
ベルの時ｄ＠に切換わる機構威されている。又、フＶツ
ブフロップｒｒｑスチルモード開始スイッチＳＷ２をＯ
Ｎする事によ）セットされる様・図の如く構成されてい
る。又８Ｗ１は連続モード開始スイッチでＯＮする事に
よ伽曽記モータ制御回路ＲＭＣが始動される。The output of the one-shot circuit 083 is inputted to the reset terminal of the tree frog FF through a one-shot circuit with fall polysynchronous. GH is a note related to this IA@.
In the playback head, the scissors head is the flip foots 1Fr#
) While the Ql force is at a low level, the video output of the recording signal section 11HIIP82 can be recorded to a predetermined quadrature of the magnetic disc D through the switch 8W5, and the Q output of the flip 7a is at a high level. In this case, by switching to the side, the reproduced video signal is transferred to the playback signal L & ring circuit P85i (guided), and this can be monitored by the monitor device MTVK via the switch 8W4.Note 1 The switches 8W5 to 8W5 have a mechanism that switches to the e side when the above-mentioned switching block flop FFF)Q output is at a high level, and to the d@ side when it is at a low level. Also, turn the flop rrq still mode start switch SW2 to O.
It is configured as shown in the figure. Further, when 8W1 is turned on with the continuous mode start switch, the Goseki motor control circuit RMC is started.
尚、前記アンド回路ムＮＤの残りの入力端には前記ツリ
ツブフロッグのＱ出力が接続されていミス、シーケンス
制御回路８ＣＴＬは本発明のスチルモードにおいて前記
同期信号１発生回路８ＹＮＣの代わシにドライバー回路
ＤＢＩＫ駆動制御信号を出力すると共に連続壁−ドにお
いてシフトモータ制御回路により同期的にヘッドＲＨを
シフトする為の同期信号を供給する。Note that the remaining input terminal of the AND circuit ND is connected to the Q output of the Treetubfrog, and the sequence control circuit 8CTL is used as a driver in place of the synchronization signal 1 generation circuit 8YNC in the still mode of the present invention. The circuit DBIK outputs a drive control signal and also supplies a synchronization signal for synchronously shifting the head RH by a shift motor control circuit in the continuous wall drive.
次ＫＩ１１図示ブロック図の動作を第１〜第４図に基づ
き説明する。連続量−ドスイッチＳＷ１をＯＮすると、
毫−ター制御翻路ＲＭＣが始動されディスクＤの回転が
開始されると共に撮像系等が駆動され、同期信号発生回
路８ＹＮＣから紘同期信号が例えば第２図示の如く周期
Ｔ・で出力される。Next, the operation of the illustrated block diagram of KI11 will be explained based on FIGS. 1 to 4. When the continuous quantity switch SW1 is turned on,
The camera control circuit RMC is started and the rotation of the disk D is started, and at the same time, the imaging system and the like are driven, and a synchronization signal is outputted from the synchronization signal generation circuit 8YNC at a period T, for example, as shown in the second diagram.
この周期テ・轄例えばＶ醜秒に設定する。そしてこの同
期信号はスイッチ８Ｗｓを介してドライバー回路ＤＲ１
に供給され、第２目示の様なパルスφｌ〜−８が生成さ
れる。即ち、Φ１社受光部ｌ内の電荷を蓄積部８に転送
する転送パルス、ΦＳは蓄積部８の電荷を水平レジスタ
ーＨＲに転送する転送パルス％＃Ｉｍ水平レジスタ）１
Ｒ内の電荷を出力７ングムＭ（読み出す為の水平タロッ
クパ゛ルスである。This period is set to, for example, V second. This synchronization signal is then passed through the switch 8Ws to the driver circuit DR1.
, and pulses φl to −8 as shown in the second indication are generated. That is, Φ1 is a transfer pulse that transfers the charge in the light receiving section l to the storage section 8, and ΦS is a transfer pulse that transfers the charge in the storage section 8 to the horizontal register HR (%#Im horizontal register) 1
The charge in R is output 7 nm (horizontal tally pulse for reading).
崗、第４Ｅ示撮像素子は水平レジスタＨＲの近傍にオー
バー７０−ドレインＯＦＤが設けてあシ、水平レジスタ
との間の障壁社アンチブルー建ングバマア構造となって
いる為、パルスΦ魯による読み出しを行なわすにΦ１．
φＩＫよる転送のみを行なうと過剰電荷社水平レジスタ
からオーバー７ ａ −ドレインに吸収される。The 4th E image sensor has an over 70-drain OFD near the horizontal register HR, and has an anti-blue barrier structure between it and the horizontal register, so readout by pulse ΦL is possible. Φ1.
If only transfer by φIK is performed, excess charge is absorbed from the horizontal register to the over7a-drain.
尚、第２図示の如仏時間Ｔ４中に受光部ＩＫ蓄積された
電荷は同期信号のハイレイル期閲〒＠”？にパルスΦ１
．Φ３により蓄積部８に転送され、次のローレベル期ｌ
５ｌｌＴ番中に、パルスφ―、・ｓＫ！！水平レジスタ
に・′１行ずつシフトされて読み出される・そして、こ
の読み出された信号はプロセス回路Ｐ ８１ 、ｗ ）
リツクス回路Ｍ’ｌ”Ｘ、スイッチ駒のｄ＠を介してモ
ニター装置ＭＴＶＫ供給されると共に、配録信号処理１
１１１Ｐ８２％スイッチ８Ｗ５のｄ側、ヘッドＧＨを介
して回転ディスクの所定トラックに繰り返し記鎌される
。尚モータ制御回路ＲＭＣによ多ディスタの回転周期が
前記同期信号の周期Ｔ・と同じか或いは整数倍になるＳ
！賂薯餉制御籠ている。又、記帰再生ヘッドＧＨの前方
同一トラック上等には消去ヘッドが設けである。Incidentally, the charge accumulated in the light receiving section IK during the Buddha time T4 shown in the second figure is generated by the pulse Φ1 in the high rail period of the synchronization signal 〒@''?
．． Transferred to the storage section 8 by Φ3, and stored in the next low level period l
During the 5llT turn, the pulse φ-, sK! ! The signal is shifted to the horizontal register and read out one row at a time.Then, this read signal is sent to the process circuit P 81 , w )
The monitor device MTVK is supplied via the logic circuit M'l''
The signal is repeatedly recorded on a predetermined track of the rotating disk via the d side of the 111P82% switch 8W5 and the head GH. In addition, in the motor control circuit RMC, the rotation period of the multidistor is the same as the period T of the synchronization signal, or is an integral multiple of the period S.
! The bribes are under control. Further, an erasing head is provided on the same track in front of the recording/reproducing head GH.
又、この連続モード状態において例えばマ）！クス回路
ＭＴＸｆ）Ｙ信号出力社、同期信号の文下り毎にリセッ
トされる積分回路’Ｉ Ｇによ多周期的に積分され、該
積分出力はこのリセット直前、即ち同期信号の立上）毎
にサンプルされ次の、サンプ９ｙ／迄の間ホールドされ
る。従ってこのサンプルホールド回路出力社周期Ｔ・分
だけ実時間から遅れて嬬いるがＴＴＬｉｌ光値に相当す
るものである。Also, in this continuous mode state, for example, Ma)! Multi-periodic integration is performed by the integrator circuit 'IG, which is reset every time the synchronization signal goes down, and the integral output is output just before this reset, that is, every time the synchronization signal rises. It is sampled and held until the next sampling 9y/. Therefore, the output of this sample-and-hold circuit is delayed from the real time by the period T minutes, but corresponds to the TTLil light value.
この−光値Ｅを演算回路ＯＰに入力する事によ多ＩＮ端
子からの入力情報と演算し、第６図に示す橡な組み合わ
せ出力を端子ム、Ｂよに出力する。By inputting this -light value E to the arithmetic circuit OP, it is operated on with the input information from the multi-IN terminal, and an elegant combination output shown in FIG. 6 is outputted to the terminals M and B.
又このム、Ｂ端からの出力社夫々例えばムＰＢＸ方式の
演算により得られるムマ、Ｔｖ４（相当する様な信号で
ある。又ｓ”’−１＃ｉ変数を示す。In addition, the output signals from the B terminal are signals such as Tv4 and Tv4 obtained by calculation of the PBX system, respectively. Also, s'''-1#i variables are shown.
崗、演算回路ＯＰの各コントロール入力端鳳。Each control input end of the control circuit and the arithmetic circuit OP.
ｂ、ｃｌｃｄ夫々、第５図の如き論理入力が連続モード
指示回路ＣＤｘ嬬モードセレクメＭＳから入力される。Logic inputs as shown in FIG. 5 are inputted from the continuous mode instruction circuit CDx and the mode selector MS for each of b and clcd.
例えば、連続モードスイッチ８Ｗ１がＯＮ、スチールモ
ードスイッチｓｗ２がＯＦＦ。For example, the continuous mode switch 8W1 is ON and the steel mode switch sw2 is OFF.
即ち連続モードの場合にはグー）０５が開き、ゲートＧ
４−が閉じるので、回路ＣＤの出力値（０１０）が入
力端１〜Ｃに供給される。これにより第３図示の如く入
端子から轄ムマに対応する信号が出力されて絞９ムＰを
制御する。又％Ｂ端子からの出力社無い。この様に連続
モード時にはすンプルネールドされた測光値に基づき絞
）が制御されると共に、撮ｇＩ票子の蓄積時間は時間Ｔ
＊１（ｌｊｌ定される。That is, in the case of continuous mode, gate G)05 is opened and gate G
4- is closed, the output value (010) of the circuit CD is supplied to the input terminals 1-C. As a result, as shown in FIG. 3, a signal corresponding to the diaphragm is output from the input terminal to control the diaphragm 9P. Also, there is no output from the %B terminal. In this way, in the continuous mode, the aperture (aperture) is controlled based on the photometric value that has been simply nailed, and the accumulation time of the shooting gI tag is the time T.
*1 (ljl is determined.
そして前述の如く、映倫信号はモニターされると共に、
所定のフィールドメモリー用のトラックに記録される。As mentioned above, the Eirin signal is monitored and
Recorded on a predetermined field memory track.
又１１フイールド毎に順次トラックを切換えながら記録
ヘッドＲＨＫよ）動画を配置していく。Also, moving images are placed on the recording head RHK while sequentially switching tracks every 11 fields.
次に予めモードセレクタＭ８により第ＳｖＡ示の適宜モ
ードを選択すると共にｓｇｌ、ｓｍＨｃより適宜の蓄積
時間、絞）等を設定した後スチールモードスイッチＳＷ
２をＯＮすると、アリツブフロップＦＦがセットされる
ので演算回路ＯＰ ｆ） 漏ントロール入力ａ〜０」セ
レクタＭ８からのデータが入力され、これに応じてＦＦ
ｔｒ）Ｑ出力がハイレベルとな゛る事によ畳アントゲー
トムＮＤが閉じられナングルホールド回路１８ＨＣにお
けるナンプリン／Ｆｉ停止し、連続そ−ドにおける１１
党光値が保持される。又、８Ｗ５〜８Ｗ５が・儒に切換
わるので先ずアリツブフロップＦＦのセットによ参ジー
タンス制御回路にて生成された信号によりドツィλ−１
路ＤＲｉが駆動パルス＃１．Φ烏を第２ａ！３の如く供
給する。これＫよ多受光部ｌ内の不要電荷かクリアされ
る。又、カウンタＣＮＴがリセットされ、予め選択され
たモード及び設定値に応じた蓄積時間７１１が経過する
とＣ端子からパルスが出力され、これがジ−タンス制御
回路８ＣＴＬに入力されてドライバー回路ＤＲ１を介し
て撮儂素子の受光部から蓄積部への電荷の転送及び蓄積
部からの絖み出しパルスφ鳳〜＃ｌによ＊＊紬され為・
又％オクンタＣＮテのＣ端子からのパルスの文上参に同
期してワンシ冒ット回路０８６が第２図示のパルス巾テ
懲のパルスを出カシ、この間マグネットが作動してシャ
ッタが閉じ受光部への光入射を阻止する。これによ）少
なくとも受光部ｌから蓄積＠ａへの電荷転送期間（Ｔｓ
）中は党が入射を閉じる様にしているが、これはシャッ
タの応答をＴｓ’の如く極めて短時間にするのが困難で
あるのと、時間Ｔｓ’以上であっても何ら差支えがない
為である。又、本実施例では撮曹嵩子からの信号の読出
し終了稜速やかにスチルモールドから連続毫−ドに後帰
させる為の７リツプ７０ツブＦＦの９セット信号をとの
ワンシ璽ット回路Ｏ８３の立下参に同期してワンシｌッ
ト０８４によ）形成しているので、シャッタ閉成時間Ｔ
愈は読出しに要する全体の時間〒・以上にするのが望ま
しい。何故なら余）早（連続モードに後彎するとスチル
モード２の信号読み出し中に新たな画像が蓄積部に転送
されてしまう恐れがある為である。尚、本実施例ではＴ
・−Ｔｓとしである。又、本実施例ではスイッチ８Ｗ２
によるスチルモード撮影状アリツブフロッグのリセット
入力が入る迄は、たとえスイッチ８Ｗ２が一瞬しかＯＮ
Ｌな（でも保持される様為されている。Next, after selecting the appropriate mode shown in SvA using the mode selector M8 and setting the appropriate accumulation time, aperture), etc. from sgl and smHc, the steel mode switch SW
When 2 is turned on, the Aritsubu flop FF is set, so the arithmetic circuit OP f) Leakage control input a~0'' data from the selector M8 is input, and the FF is set accordingly.
tr) When the Q output becomes high level, the folding gate gate ND is closed, the number print/Fi in the nangle hold circuit 18HC is stopped, and the 11 in the continuous code is stopped.
Party light value is retained. In addition, since 8W5 to 8W5 are switched to -1, first set the Aritz flop FF and use the signal generated by the reference Geetance control circuit to set Dots λ-1.
The path DRi is the drive pulse #1. The Φ crow is the second a! Supply as in 3. This clears unnecessary charges in the multi-light receiving section l. Further, when the counter CNT is reset and the accumulation time 711 corresponding to the preselected mode and set value has elapsed, a pulse is output from the C terminal, which is input to the jitance control circuit 8CTL and passed through the driver circuit DR1. Transfer of electric charge from the light receiving part of the photo-sensing element to the storage part and the start-up pulse from the storage part.
In addition, in synchronization with the output of the pulse from the C terminal of the %ocunta CNte, the one-shot circuit 086 outputs a pulse with the pulse width shown in the second diagram, and during this time the magnet operates and the shutter closes to receive light. Prevents light from entering the area. As a result, at least the charge transfer period (Ts
), the entrance is closed by the shutter, but this is because it is difficult to make the shutter response as extremely short as Ts', and there is no problem even if the shutter response is longer than Ts'. It is. In addition, in this embodiment, the one-shot circuit O83 is activated to send a 9-set signal of 7-rip, 70-tube FF in order to quickly return from the still mold to the continuous screen after reading out the signal from the sensor. The shutter closing time T
It is desirable that the total time required for reading out is equal to or longer than 〒·. This is because if you switch to continuous mode too early, there is a risk that a new image will be transferred to the storage section while the signal is being read in still mode 2.In this example, T
・-Ts. Also, in this embodiment, the switch 8W2
Even if switch 8W2 is ON for only a moment until the reset input is input for the still mode shooting mode,
L (but it seems to be retained.
又、スイッチＳＷ２のＯＮによって、それ迄マトリクス
回路ＭＴＸからモニター装置に供給されていた映偉信号
は、連続モード中に１フイールドずつ更新して記録され
ていた信号の再生出力に切示し続け、−面が消えたり乱
れたシする事がない。Also, by turning on the switch SW2, the video signal that had been supplied to the monitor device from the matrix circuit MTX until then continues to be output as the reproduction output of the signal that was updated field by field during the continuous mode, and - The surface will not disappear or become disordered.
崗、本実施例でＦｉミツイールドメモリして磁気ディス
クの所足のトラツタを用いているが、本発＠轄この橡な
アナログメモリに限定されるもので轄なく、！トリクス
回路出力を常時ムθ変換してからデジタルメモリを一時
記憶し、１フイールド毎にこれを更新して行くよ５Ｋし
ても達成し得る。In this embodiment, we use a magnetic disk as a Fimit yielded memory, but this is not limited to analog memory, and is not limited to this! This can also be achieved by constantly converting the output of the TRIX circuit into 5K, temporarily storing it in a digital memory, and updating it every field.
この場合スチルモードに＠換えられる事によりメモリの
内容なり、４変換してモニタに導びく様にすれば嵐い。In this case, the contents of the memory can be changed to still mode, and it would be great if you could convert it to 4 and lead it to the monitor.
又、本実施例ではＹ信号を！トリクス回路の出力から得
ているが、プロセス回路の出力を合成して得て−良い。Also, in this embodiment, the Y signal! It is obtained from the output of the trix circuit, but it can also be obtained by combining the output of the process circuit.
撮像素子の受光部の一部をａｔ党専用とし１ここからの
出力を積分する事によ参−光値を得て４ＪＬい。A part of the light-receiving part of the image sensor is dedicated to AT, and the reference light value is obtained by integrating the output from this part.
崗、撮像手段としては第４Ｎ示の如きフレー＾トランス
ファー１１ｃｃＤに限られるものではなくインターライ
ントラン、スファー型のものであっても嵐い。However, the imaging means is not limited to a frame transfer 11ccD as shown in No. 4N, but may also be an interline transformer or a spacer type.
ｓ１１図は本発明の撮像装置の一実施例のブロック図、
第２図は第１図示回路の要部タインンダ図、第６図社演
算回路ＯＰの入出力状１１１図、第４図紘本発明に適用
される撮像素子の一例を示す図であるＯ
ムＰ ４１＠・■絞り手段、８Ｈ’ｒ、・・・・シャッ
タ手段％ｌＤ０・拳・撮像素子、Ｄｉａ１．．・・・ド
ライバー回路％ｌ Ｑ ＠ＩＩ＠拳・積分回路、８ＨＣ
＠＠・・・ナンプ々ホールド回路、ＱＨ＠−・・・メモ
リー書込み読めし用ヘッド、ＭＴＶ・・・・・モニター
装置、ＯＰ・・・■演算回路。
特許田麩 キャノン株式会社
町島μs11 is a block diagram of an embodiment of the imaging device of the present invention,
FIG. 2 is a diagram showing the principal parts of the circuit shown in FIG. 1, FIG. 6 is an input/output diagram of the arithmetic circuit OP, and FIG. 4 is a diagram showing an example of an image sensor applied to the present invention. 41@・■ Aperture means, 8H'r, ... Shutter means %lD0・Fist・Image sensor, Dia1. ．． ...Driver circuit%l Q @II@Fist/integral circuit, 8HC
@@...Number hold circuit, [email protected] write/read head, MTV...Monitor device, OP...■ Arithmetic circuit. Patented rice cake Canon Co., Ltd. Machijima μ
Claims (1)
る保持手段と、 該保持手段の保持出力を周期的に更新する更新手段と、 前記保持手段の出力に応じて露出制御を行う露出制御手
段と、 前記撮侭手段の走査を前記周期に拘らず開始するトリガ
一手段と、 諌トリガ一手段による走査開始に伴ない前記更新手段の
周期的な更新を停止する停止゛手段とを有する撮像装置
。[Claims] Holding means for holding a part of the output from the imaging means that is periodically scanned; updating means for periodically updating the holding output of the holding means; and according to the output of the holding means. exposure control means that performs exposure control based on exposure control; a trigger means that starts scanning of the photographing stop means regardless of the period; and a trigger means that stops periodic updating of the update means upon the start of scanning by the trigger means. An imaging device having a stop means.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56215342A JPS58116880A (en) | 1981-12-29 | 1981-12-29 | Image pickup device |
| US06/452,500 US4599657A (en) | 1981-12-29 | 1982-12-23 | Image pick-up device |
| US06/860,513 US4763204A (en) | 1981-12-29 | 1986-05-07 | Solid state image pick-up device having a shutter which is capable of still and motion picture photography |
| US07/274,703 US4910606A (en) | 1981-12-29 | 1988-11-15 | Solid state pick-up having particular exposure and read-out control |
| US07/459,564 US5010418A (en) | 1981-12-29 | 1990-01-02 | Image pick-up device |
| US07/654,802 US5309247A (en) | 1981-12-29 | 1991-02-13 | Image pick-up device |
| US08/073,648 US5760830A (en) | 1981-12-29 | 1993-06-08 | Image pick-up device having switching over means, image pick-up means, monitor means, recording means, still picture display means and control means |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56215342A JPS58116880A (en) | 1981-12-29 | 1981-12-29 | Image pickup device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58116880A true JPS58116880A (en) | 1983-07-12 |
| JPH0230633B2 JPH0230633B2 (en) | 1990-07-09 |
Family
ID=16670708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56215342A Granted JPS58116880A (en) | 1981-12-29 | 1981-12-29 | Image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58116880A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58117778A (en) * | 1981-12-30 | 1983-07-13 | Sony Corp | Solid-state image pickup device |
| JPS58117775A (en) * | 1981-12-30 | 1983-07-13 | Sony Corp | Image pickup device |
| EP0272307B1 (en) * | 1986-06-30 | 1992-05-06 | EASTMAN KODAK COMPANY (a New Jersey corporation) | Exposure control apparatus for a still video camera having an electronic viewfinder |
| JPH05344794A (en) * | 1991-03-06 | 1993-12-24 | Daikin Ind Ltd | Malfunction detector for driving circuit |
| JPH06113593A (en) * | 1990-12-29 | 1994-04-22 | Daikin Ind Ltd | Abnormality detector for step motor circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4398389B2 (en) | 2005-02-03 | 2010-01-13 | 富士フイルム株式会社 | Imaging device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5480124A (en) * | 1977-12-09 | 1979-06-26 | Minolta Camera Co Ltd | Camera with automatic focus control device |
| JPS55165077A (en) * | 1979-06-12 | 1980-12-23 | Fuji Photo Film Co Ltd | Video camera in common use for still and movie |
-
1981
- 1981-12-29 JP JP56215342A patent/JPS58116880A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5480124A (en) * | 1977-12-09 | 1979-06-26 | Minolta Camera Co Ltd | Camera with automatic focus control device |
| JPS55165077A (en) * | 1979-06-12 | 1980-12-23 | Fuji Photo Film Co Ltd | Video camera in common use for still and movie |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58117778A (en) * | 1981-12-30 | 1983-07-13 | Sony Corp | Solid-state image pickup device |
| JPS58117775A (en) * | 1981-12-30 | 1983-07-13 | Sony Corp | Image pickup device |
| JPH0320110B2 (en) * | 1981-12-30 | 1991-03-18 | Sony Corp | |
| JPH0320109B2 (en) * | 1981-12-30 | 1991-03-18 | Sony Corp | |
| EP0272307B1 (en) * | 1986-06-30 | 1992-05-06 | EASTMAN KODAK COMPANY (a New Jersey corporation) | Exposure control apparatus for a still video camera having an electronic viewfinder |
| JPH06113593A (en) * | 1990-12-29 | 1994-04-22 | Daikin Ind Ltd | Abnormality detector for step motor circuit |
| JPH05344794A (en) * | 1991-03-06 | 1993-12-24 | Daikin Ind Ltd | Malfunction detector for driving circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0230633B2 (en) | 1990-07-09 |
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