JPS58115844A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58115844A
JPS58115844A JP21121281A JP21121281A JPS58115844A JP S58115844 A JPS58115844 A JP S58115844A JP 21121281 A JP21121281 A JP 21121281A JP 21121281 A JP21121281 A JP 21121281A JP S58115844 A JPS58115844 A JP S58115844A
Authority
JP
Japan
Prior art keywords
output
transistors
input
gate
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21121281A
Other languages
Japanese (ja)
Other versions
JPH0243343B2 (en
Inventor
Kazumasa Nawata
名和田　一正
Toshiaki Sakai
酒井　敏昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21121281A priority Critical patent/JPS58115844A/en
Publication of JPS58115844A publication Critical patent/JPS58115844A/en
Publication of JPH0243343B2 publication Critical patent/JPH0243343B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance the duty cycle of the element and to attain prevention of electrostatic destruction of the semiconductor device by a method wherein an excess tansistor out of transistors is connected as the diode for prevention of electrostatic destruction to a wiring between an input pad out of input/output pads and a gate. CONSTITUTION:Gates or cells 4 of the necessary number are formed inside of the place arranged with the transistors for output, and the transistors 6 for output are connected between output circuits for gates and the output pads, pad 5 for example. Out of the transistors for output connected by this way, and moreover out of the transistors for output not supplied for constitution of circuit, the transistors 3 for output in the neighborhood of the input pad and fell into disuse is connected in diode connection to the wiring 7 between the input pad 6 and the gate 4. The terminal 8 of the transistor 3 connected in diode connection thereof on the opposite side to the connecting edge to the wiring 7 is connected to the previously decided reference voltage, earth potential for example, when the gate is the type to be operated by a negative driving voltage, for example.

Description

【発明の詳細な説明】 （１）８発明の技術分野 本発明はマスタースライス方式の半導体装置に係り、入
出力パッド数以上の個数形成された出力用トランジスタ
のうちの便用に供されないトランジスタを静電破壊防止
用ダイｔｏｙ！−ドとして用いた半導体装置Ｋｍする。Detailed Description of the Invention (1) 8 Technical Fields of the Invention The present invention relates to a master slice type semiconductor device, in which a transistor that is not used for use among output transistors formed in a number greater than the number of input/output pads is removed. Die toy for preventing electrostatic damage! - The semiconductor device used as a board is Km.

（２＞　　発明の背景 半導体チップに形成されたマスタースライス方式の半導
体装置けその集積密度が高められるにつれて、その集積
回路パターンはますます微細化される傾向にある。その
ため、その集積回路素子の静電破壊耐圧が低下するので
、その対策が講じられねばならなくなって来ている。(2> Background of the Invention As the integration density of master slice semiconductor devices formed on semiconductor chips increases, the integrated circuit patterns tend to become finer and finer. Since the electric breakdown voltage is lowered, countermeasures have to be taken.

（３）、従来技術と問題点 このような要請に応える手段として、そのための特別の
素子乃至回路を集積回路内に設けることも考えられるが
、このような素子乃至回路によって素子の静電破壊も防
止しうることＫなる代りに、これらの素子乃至回路によ
って、切角集積密度を高めようとした企図とは裏腹の結
果が出てしまうという不具合がある。(3) Prior Art and Problems As a means to meet these demands, it may be possible to provide special elements or circuits within the integrated circuit for this purpose, but such elements or circuits may cause electrostatic damage to the elements. Although this can be prevented, there is a problem in that these elements or circuits produce results that are contrary to the intention of increasing the angular integration density.

（４）、発明の目的 本発明はこのような不具合に鑑みて創案されたもので、
その目的は集積密度を低下させることなく、素子の使用
率を高めっ＼、しかも静電破壊防止をも達成しうる半導
体装置を提供することＫある。(4), Purpose of the Invention The present invention was devised in view of the above-mentioned problems.
The purpose is to provide a semiconductor device that can increase the usage rate of elements without reducing the integration density, and can also prevent electrostatic damage.

（５）１発明の構成 そして、この目的は半導体チップ周囲に設けられた入出
力パッドと内部ゲートとの間に人出カバラド数に等しい
か又はよ勢多い出力用トランジスタを予め設け、そのト
ランジスタの内の余分となるトランジスタを入出カッ（
ラドのうちの入力パッドとゲートとの間の配＠に静電破
壊防止用ダイオードとして接続することＫよって達成さ
れる。(5) 1 Structure of the Invention The purpose of this invention is to provide in advance output transistors equal to or greater than the number of Kabarads between the input/output pads provided around the semiconductor chip and the internal gates. Input/output the extra transistor inside (
This is achieved by connecting a diode for preventing electrostatic damage to the wiring between the input pad and the gate of the pad.

（６）０発明の実施例 以下、添付図面を参照して本発明の詳細な説明する。(6) Example of 0 invention Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

添付図面は本発明の実施例を示す。１は半導体チップで
、その周囲に入出力／＜ラド２が配設されている。これ
ら入出力パッドの内側に出力用トランジスタ３が予め設
けられる。一般にマスタースライス方式での回路構成で
は、その自由度を高めるため、マスターノくターンでの
トランジスタ３の数は入出カッ（ラド（ピン）数以上と
される。これら出力用トランジスタが配設されている内
側に％所要数のゲート乃至セル４が形成されている。The accompanying drawings illustrate embodiments of the invention. Reference numeral 1 denotes a semiconductor chip, around which input/output/<rad 2 is arranged. Output transistors 3 are provided in advance inside these input/output pads. Generally, in a circuit configuration using the master slice method, in order to increase the degree of freedom, the number of transistors 3 in the master node is set to be greater than the number of input/output pins. A required number of gates or cells 4 are formed inside the gate.

そして、これらゲートの出力回路と化カッくラド、例え
ば５との関に出力用トランジスタ６が接続される。An output transistor 6 is connected between the output circuit of these gates and a circuit board, for example 5.

仁のようＫして接続された出力用トランジスタの外、回
路構成に供されなかった出力用トランジスタのうちの、
入力パッド近傍にある、余分となった出力用トランジス
タ３が入力／くラド６とゲート４との間の配線７にダイ
オード接続されて接続される。このダイオード接続のト
ランジスタ３の配＄７への接続端とは反対側の端子８は
、ゲートが例えば負の駆動電圧で動作される形式のもの
であるとし九場合、予め決められ九基準電圧例えば大地
電位へ接続される。Of the output transistors that were not used in the circuit configuration, in addition to the output transistors that were connected in a similar manner,
The redundant output transistor 3 located near the input pad is diode-connected to the wiring 7 between the input/cladding 6 and the gate 4. The terminal 8 of this diode-connected transistor 3 opposite the connection end to the wiring 7 is connected to a predetermined reference voltage, e.g. Connected to earth potential.

このようなダイオード接続の出力用トランジスタの、入
力パッドとゲートとの間の配線への接続は必要とする入
力パッド毎に施される。Connection of such a diode-connected output transistor to the wiring between the input pad and the gate is performed for each required input pad.

とのような回路構成にすると、入カッ（ラドからサージ
等の異常電圧が入っても、ダイオード＃続のトランジス
タ３の容量成分が上記異常電圧に作用してこれを入力ゲ
ートに緩和して給与せしめるから、微細化して静電破壊
耐圧の低下している入力ゲート４に静電破壊を生ぜしめ
るのを防止することが出来る。このような静電破壊耐圧
性の強化は上述の如きダイオード接続のトランジスタの
数を増すととＫよって達成される。このようなトランジ
スタは入力パッド近くＫあるのでその接続が容易である
。With a circuit configuration like this, even if an abnormal voltage such as a surge enters from the input voltage, the capacitance component of the transistor 3 connected to the diode acts on the abnormal voltage and relieves it and supplies it to the input gate. Therefore, it is possible to prevent electrostatic damage from occurring in the input gate 4, whose electrostatic breakdown voltage has decreased due to miniaturization.This enhancement of the electrostatic breakdown voltage can be achieved by using diode connections as described above. This can be achieved by increasing the number of transistors. Since such transistors are located near the input pad, their connection is easy.

このような静電破壊耐圧性の強化は予めチップ上に形成
されている出力用トランジスタを用いて達成されるから
、チップ上の素子の使用率を高めるととＫなるし、集積
回路の微細化を推進させ得ることにもなる。This type of enhancement of electrostatic breakdown voltage is achieved by using output transistors that are formed on the chip in advance, so increasing the usage rate of elements on the chip will cost K, and the miniaturization of integrated circuits will increase the usage rate of the elements on the chip. It will also be possible to promote the

（７）　　発明の効果 以上の説明から明らかなように１本発＠によれば、予め
形成されている出力用トランジスタを静電破壊防止用ダ
イオードとして用いているので素子使用率が向上し、そ
のダイオードによる静電破壊耐圧性の強化により、集積
回路の微細化を更に推進させ得ることとなる。そして、
このような利点は上記ダイオードの増加の許される限度
において、容易に増強すると々が可能である。また、上
述の効果は上述ダイオード接続の容品性が得られる中で
獲得される轡の優れた効果を享受出来る。(7) Effects of the invention As is clear from the above explanation, according to the one-shot @, the pre-formed output transistor is used as a diode to prevent electrostatic damage, so the element usage rate is improved and the By strengthening the electrostatic breakdown voltage with diodes, it will be possible to further promote the miniaturization of integrated circuits. and,
Such advantages can be easily enhanced within the permissible increase in the number of diodes. In addition, the above-mentioned effects can be enjoyed while the above-mentioned diode connection has the excellent properties of the capacitor.

【図面の簡単な説明】[Brief explanation of the drawing]

添付図面は本発明の実施例を示す図である９゜図中％ｌ
は半導体チップ％２は入出力パッド、４はゲート、６は
入出力パッドのうちの入力パッド、３は出力用トランジ
スタ、７は配線である。 特許出願人　富士通株式会社The attached drawings are diagrams showing embodiments of the present invention.
is a semiconductor chip % 2 is an input/output pad, 4 is a gate, 6 is an input pad of the input/output pads, 3 is an output transistor, and 7 is a wiring. Patent applicant Fujitsu Limited

Claims (1)

【特許請求の範囲】[Claims] 半導体チップ周囲に入出力パッドを有し、その内側に複
数のゲートを設けて成るマスタースライス方式の半導体
装置において、上記入出力パッドの数以上の出力用トラ
ンジスタを上記入出力パッドとゲートとの関に設け、上
記入出力パッドのうちの入力パッドとゲートとを接続す
６配線に％上記出力用トランジスタの内の使用に供され
ないトランジスタを静電破壊防止用ダイオードとして接
続したことを特徴とする半導体装置。In a master slice type semiconductor device that has input/output pads around a semiconductor chip and a plurality of gates inside the semiconductor chip, a number of output transistors greater than the number of input/output pads are connected to the input/output pads and gates. A semiconductor characterized in that an unused transistor among the output transistors is connected as a diode for preventing electrostatic damage to six wirings connecting the input pad and the gate of the input/output pad. Device.
JP21121281A 1981-12-28 1981-12-28 Semiconductor device Granted JPS58115844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21121281A JPS58115844A (en) 1981-12-28 1981-12-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21121281A JPS58115844A (en) 1981-12-28 1981-12-28 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS58115844A true JPS58115844A (en) 1983-07-09
JPH0243343B2 JPH0243343B2 (en) 1990-09-28

Family

ID=16602167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21121281A Granted JPS58115844A (en) 1981-12-28 1981-12-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58115844A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208771A (en) * 1983-05-13 1984-11-27 Hitachi Ltd Semiconductor integrated circuit device
JPS6146046A (en) * 1984-08-10 1986-03-06 Hitachi Ltd Semiconductor integrated circuit device
US4918563A (en) * 1983-09-22 1990-04-17 Fujitsu Limited ECL gate array semiconductor device with protective elements

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181152A (en) * 1981-04-30 1982-11-08 Toshiba Corp Semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181152A (en) * 1981-04-30 1982-11-08 Toshiba Corp Semiconductor integrated circuit device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208771A (en) * 1983-05-13 1984-11-27 Hitachi Ltd Semiconductor integrated circuit device
JPH0439785B2 (en) * 1983-05-13 1992-06-30
US4918563A (en) * 1983-09-22 1990-04-17 Fujitsu Limited ECL gate array semiconductor device with protective elements
JPS6146046A (en) * 1984-08-10 1986-03-06 Hitachi Ltd Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPH0243343B2 (en) 1990-09-28

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