JPS58114396A - Nonvolatile memory - Google Patents
Nonvolatile memoryInfo
- Publication number
- JPS58114396A JPS58114396A JP56213616A JP21361681A JPS58114396A JP S58114396 A JPS58114396 A JP S58114396A JP 56213616 A JP56213616 A JP 56213616A JP 21361681 A JP21361681 A JP 21361681A JP S58114396 A JPS58114396 A JP S58114396A
- Authority
- JP
- Japan
- Prior art keywords
- potential
- transistor
- type transistor
- node
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
Landscapes
- Read Only Memory (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、外部電源として書自込み用／消去用高電位と
読み出し用電位が印加される０Ｍ０１回路をメモリーセ
ル・アレイの周辺部に有する不揮発性メモリーに関する
。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a non-volatile memory having an 0M01 circuit in the periphery of a memory cell array to which a high potential for writing/erasing and a potential for reading are applied as an external power supply. Regarding.
発明の技術的背景とその間照点
第１図はチップ上にあるメモリーセル・アレイ以外の周
辺回路が、ＮチャネルＭ／Ｄ （エン／Ｓンスメント／
デデレッシ、ン） ｌｉｔ ｙｏｓ回路である不揮発性
メモリーの従来の書き込み用高電位。Technical Background of the Invention and Points of Interest Figure 1 shows that the peripheral circuits other than the memory cell array on the chip are N-channel M/D
Conventional high potential for writing in non-volatile memory, which is a lit yos circuit.
読み出し用電位切シ換えスイッチ部を示している。ここ
でデデレ、シ、ン型トランジスタ１１゜１２０閾値電圧
は約″″−３ｖ”である。を良書き込み用高電位Ｖ。の
節点１には２０ｖ、貌与出し用電位ｖｃｃＯ穎点２には
５ｖが印加されている。いま節点４を■。、節点３を０
（零）Ｖにすれば、電位切シ換え節点５は略■。になる
。A read potential changeover switch section is shown. Here, the threshold voltage of the thin-type transistor 11°120 is approximately ``''-3V''.The high potential for good writing V is 20V at node 1, and the potential for writing is 20V at node 2. 5V is applied.Now, node 4 is set to ■., node 3 is set to 0.
If it is set to (zero) V, the potential switching node 5 is approximately ■. become.
逆に節点４をＯｖ１節点３′ｔ−ｖＰＰの電位にすれば
、切り換え節点５は略ｖＰＰになる。このようにしてＤ
ｌｌｌ）ランジスタｔｉ、ｉｓを用いれば、電位切〉換
えスイッチ回路は容易に実現できる。Conversely, if node 4 is set to the potential of Ov1 node 3't-vPP, switching node 5 becomes approximately vPP. In this way D
ll) By using transistors ti and is, a potential switching circuit can be easily realized.
しかしながら、ノタワー節約のために周辺回路ＩｃＭｏ
ｇｉ（相補製ＭＯ８）構成にしたときには、Ｄｆｉ）ラ
ンジスタは閾値を１個増すことでＰＥＰ（′Ｉ＃真蝕刻
工ｌｉ）数が２回増加し、ＰｆｆｉＰ数の大きなｃｍｏ
ａの工１１を更に増加させる大きな欠点を有していた。However, in order to save power, the peripheral circuit IcMo
When the gi (complementary MO8) configuration is used, the Dfi) transistor increases the PEP ('I# true etching process li) number by two times by increasing the threshold value by one, and the cmo with a large PffiP number
This had the major drawback of further increasing the work 11 of a.
発明の目的
本発明は上記実情ＫｆＩ／１みてなされたもので、その
目的とすゐとζろは、ＣＭＯ８構成をメモリーセル・ア
レイの周辺回路にもつ不揮発性メモリーにおいて、書き
込み用高電位と読み出し用電位を、従来の問題なしにオ
ンｅチ、ゾで切り換えることができるスイッチ回路を有
した不揮発性メモリーを提供することにある。Purpose of the Invention The present invention has been made in view of the above-mentioned actual situation KfI/1, and its purpose and objectives are to provide a high potential for writing and a high potential for reading in a non-volatile memory having a CMO8 configuration in the peripheral circuit of the memory cell array. It is an object of the present invention to provide a non-volatile memory having a switch circuit which can switch the electric potential on-the-fly without the conventional problems.
発明の概要 ・
上記発−の目的を達成する九めに、本発明では電位切シ
換えスイッチに、二ンノ・ンスメント或いはＢｌ−ＭＯ
８構造を用いる。しかしＤ臘トランノスタをＥ型トラン
ジスタに単純に置自換えただけでは、上記切ル換えスイ
ッチの一方の電極とサブストレート電極間にＰＮ正バイ
アスがかかつて電流の迷流路が生じ、電位切〉換えの正
常動作が期待できない。そこで本発明では、上記ＰＮ正
バイアスがかがゐトランジスタのｔブストレート電極を
電位切勤換え陣点儒Ｋｌｉ続し、上記電流の迷流路ｔｍ
断じて正常な電位導出を行なうものである。Summary of the invention - Ninthly, in order to achieve the above-mentioned purpose, the present invention uses a potential changeover switch with a secondary voltage switch or a BL-MO switch.
8 structure is used. However, simply replacing the D-transistor with an E-type transistor causes a PN positive bias to build up between one electrode of the changeover switch and the substrate electrode, creating a stray current path, causing the potential to turn off. Normal operation cannot be expected after replacement. Therefore, in the present invention, the PN positive bias connects the t-bright electrode of the diagonal transistor to the potential switching point Kli, so that the current stray flow path tm
This ensures normal potential derivation.
発明の実施例
以下＠２図を参照して本発明の一実施例を説明する。同
図はＮチャネルＳＡＭＯ８構造をメ篭り一セルに用いた
Ｎ−Ｗ＠１１構成のＣｕＯ２ｉｉＩ Ｍをメモリー周辺
部に用いた場合の例であるが、慕１図と対応する個所に
は同一符号を用いる。Embodiment of the Invention An embodiment of the invention will be described below with reference to FIG. This figure is an example of a case where CuO2iiM with an N-W@11 configuration using an N-channel SAMO8 structure in one cell is used in the memory peripheral area. use
まず、電位切ル換えのスイッチ部２１では、書き込み／
消去用高電位Ｖ□の節点１と電位切シ換え節点５との間
にＰチャネルのｌｃ型トランジスｊｌ１２２ｔ−接続し
、読み出し用電位ｖｃ＝の節点２と節点５との間にＰチ
ャネルのＩｃＩＩ）ランノスタ２１を接続すゐ、トラン
ジスタ２２のサブストレート電極はＶ□節点ＪＫｉｌ続
し、トランジスタ２Ｊのナシストレート電極は節点５に
接続する。また電圧Ｖ□と■ｃｃｏ＠’１１８え導出を
行なう丸めの信号ｉの供給用節点２４、ｖｃｃ電位ｔｆ
ｆ−）入力とするＮチャネル型トランジスタ２５を介し
て節点Ｊ＃Ｋｌｉ続する。この節点２＃はＰチャネル蓋
トランジスタｚｙｔ介してｖＰ？節点１に接続する０節
点７ｇ＃ｉＰチャネル型トランジスタ２１、Ｎチャネル
型トラン２スタ２ｊＩよｐなるインバータの入力となシ
、＃イン・母−夕３０の一端はＶ□節点１に接続され、
他端は接地される。インバータ３０の出力端りｔ）節点
３１はトランジスタｘｉ、ｚｙのｒ−ト入力とな〉、壜
たＰチャネル蓋トランジスタＪＪ、Ｎチャネル蓋トラン
ジスタ３Ｊよりなるインバータ３４（Ｄ入力となる。イ
ンバータ３４の一端はｖＰ？節点１に接続され、他端は
接地される。ま九インバータ３４の出力端つｔシ節点Ｊ
５はトランジスタ２３のダート入力となる。First, in the potential switching switch section 21, the writing/
A P-channel lc type transistor jl122t- is connected between the node 1 of the erase high potential V□ and the potential switching node 5, and a P-channel IcII is connected between the node 2 and the node 5 of the read potential vc=. ) When the lannostar 21 is connected, the substrate electrode of the transistor 22 is connected to the V□ node JKil, and the auxiliary straight electrode of the transistor 2J is connected to the node 5. Also, a node 24 for supplying the rounded signal i for deriving the voltages V□ and ■cco@'118, vcc potential tf
f-) Connected to node J#Kli via N-channel transistor 25 serving as input. This node 2# is connected to vP? through a P-channel lid transistor zyt. 0 node 7g #i connected to node 1, P channel type transistor 21, N channel type transistor 2 jI, and the input of the inverter p, #in/mother 30 is connected to V□ node 1,
The other end is grounded. The output end of the inverter 30 (t) node 31 is the r-toinput of the transistors xi, zy), and the inverter 34 (becomes the D input) consisting of the P-channel lid transistor JJ and the N-channel lid transistor 3J. One end is connected to the vP node 1, and the other end is grounded.The output end of the inverter 34 is connected to the node J
5 becomes the dart input of the transistor 23.
８１１２図の回路動作を説明する。まず節点ＪＫＶ□電
位を発生させる場合、節点１４０信号ｉを高レベルにす
る。このとき信号■の一幅は、接地レベル（低レベル）
かうｖｃｃの高レベル資で振幅するので、はじめ節点２
６の電位は＠ｖ−ｖ ’（ｖ Ｆｉ鋼値電圧）Ｋ
ｔｋ！、ｊｃｃ ｔｈ罵 ｔｈ冨
こでインバータＪＯの回路閾値を”ＣＣ”ｉｌｌ’よ）
も低く設計しておけば、節点Ｊ１は低レベルになシ、ト
ランジスタ２１がオンして節点２６をｖ、Ｐ電位レベル
まで上昇させる。このとａ節ａｓｓのレベルは、インバ
ータ３４によフてＶ□電位まで上昇する。即ち節点１１
は低レベル、節点３５はＶ□電位となシ、トランジスタ
２２はオンして節点５はＶ□電位になる。このときトラ
ン・ゾスタ２Ｊはオフし、節点１かも節点２には直流電
流は流れない。The operation of the circuit shown in FIG. 8112 will be explained. First, when generating the node JKV□ potential, the node 140 signal i is set to high level. At this time, the width of signal ■ is the ground level (low level)
Since it oscillates at a high level of VCC, the first node 2
The potential of 6 is @v-v' (v Fi steel value voltage) K
tk! , jcc th, th Tomiko, set the circuit threshold of the inverter JO as "CC"ill')
If the voltage is also designed to be low, the node J1 will remain at a low level, and the transistor 21 will turn on, raising the node 26 to the v,P potential level. At this time, the level of the node a ass is increased to the V□ potential by the inverter 34. That is, node 11
is at a low level, node 35 is at V□ potential, transistor 22 is turned on and node 5 is at V□ potential. At this time, the Tran Zostar 2J is turned off, and no direct current flows through either node 1 or node 2.
逆に節点５にｖｃＣ電位を発生させる場合、信号Ｈｔ−
低レベルにする。このときトランジスタ２１は、前記節
点Ｊ１が低レベルであることによ如オンしているので、
トランスファｒ−）２ｊのコンダクタンスを、トランジ
スタ２１のコンダクタンスよ〉充分大きくなるように設
計する必畳がある。この工夫にし６節点２６０レベルが
インバータＪ０の閾値よ）低くなれば、節点Ｓ１は高レ
ベルとなシ、トランジスタ２１はオフとなる。このと亀
節点Ｓ５は低レベルになる。従ってトランジスタ２Ｊは
オンし、トランジスタ２２はオフする０節点５はζＯと
き、トランジスタ２３によってＶ□電位からｖｃｃ電位
に放電される。Conversely, when generating the vcC potential at node 5, the signal Ht-
make it low level. At this time, the transistor 21 is turned on because the node J1 is at a low level, so
It is necessary to design the conductance of the transfer r-)2j to be sufficiently larger than the conductance of the transistor 21. With this arrangement, if the level of the 6th node 260 becomes lower than the threshold of the inverter J0, the node S1 becomes high level and the transistor 21 is turned off. At this time, the tortoise node S5 becomes a low level. Therefore, the transistor 2J is turned on and the transistor 22 is turned off. When the 0 node 5 is ζO, the transistor 23 discharges the voltage from the V□ potential to the vcc potential.
以上のように、信号■がｖｃｃ（高レベル）のと自節点
５はｖ０レベルとな）、信号Ｈが０ｖ（ｔレベル）のと
自節点５はｖｃｃレベルとなるものである。As described above, when the signal (2) is at vcc (high level), the own node 5 is at the v0 level), and when the signal H is 0v (t level), the own node 5 is at the vcc level.
第３ＷＡは籐２図の回路を、不揮発性メモリーの本体回
路に適用した場合の例を示すｔので、号町〜ａｍｔ入力
とする列デコー〆、４＃はメモリーセル・アレイで、メ
モリーセル４＃はＳムＭＯ８構造を有している。５０１
〜ＳＯ−は列選択用トランジスタ、５ノはトランジスタ
５２〜５５よりなるトランジスタ５Ｃの制御回路、”
Ｄ ｔ ｌｌ＋Ｈ″は書き込み時に書自込み用データ入
力を＠０＃の時のみＶ□電位になル、その他詭み出し時
とかベリファイ（書き込みデータ検出）時にトランジス
タ５６をオフとする信号、Ｊｒはセンスアンプである。The 3rd WA shows an example of applying the circuit shown in Figure 2 to the main circuit of a non-volatile memory, so the column decoder inputs No. cho~amt, 4# is the memory cell array, and the memory cell 4 # has a SMMO8 structure. 501
~SO- is a column selection transistor, 5 is a control circuit for transistor 5C consisting of transistors 52 to 55,
D t ll + H'' is a signal that sets the write data input to V□ potential only when @0# during writing, and turns off the transistor 56 when reading or verifying (writing data detection). It is a sense amplifier.
第３図におけるデータ書き込みは、節点ｊＯ電位をｖＰ
Ｐにし、メモリーセルのコントロールゲートＫＶｐｐ
ｍ トラ７ノＸ１５ ｇ 、 ５０１〜Ｊ＃。Data writing in FIG. 3 is performed by setting the node jO potential to vP.
P, and the control gate of the memory cell KVpp
m tiger 7 no x 15 g, 501~J#.
を通してドレインにｖＰＰ電位が加わったメモリーセル
のみに書き込みが行なわれる。Writing is performed only to memory cells to which the vPP potential is applied to the drain through.
次に書き込み量を検出（ベリファイ）する際は、■□を
書も込み電位のｔ壕にして節点ｊをＶ 電位にすれば、
書き込み直後にセルの書自込み状態が、センスアンプ５
１を通してデータ出力部にとｐ出されるものである。Next, when detecting (verifying) the write amount, set ■□ to the write potential t trench and set node j to V potential.
Immediately after writing, the write state of the cell is determined by the sense amplifier 5.
1 to the data output section.
第２図の回路では、Ｖ□用済み後はｖＰ？電位をｖｃＣ
ＩＩ位よｐ下りることがある。−例としてｖ？？電位ｔ
−ｏｖとすると、節点５から節点１へ向りてつｔ）トラ
ンジスタ２１のソースからナラストレー）電極へ向って
順方向電流が流れ、節点５の電圧會Ｖ、電位よ〉下げて
し・壕う、そとて１１１４図に示される賓形例の如く、
１ランゾスタ２２と節点５との間ＫＰチャネル蓋トラン
ジスタ６１を介挿する。この場合節点１２が節点６の電
位よ〕下がってトランジスタ１１がオンし死時、節点１
の電位をｖｃｃよ）下げてしまう、そこでトランジスタ
６１のチャネルが形成されないように、）ランジスタロ
３．６４よシな）かりｖｃｃを電源とするインバータ６
１ｉｆ設け、その出力をトランジスタ６１の入力とする
。In the circuit shown in Figure 2, after V□ is used, vP? potential to vcC
It may go down to rank II. -For example, v? ? Potential t
-ov, a forward current flows from the node 5 to the node 1 (t) from the source of the transistor 21 to the Narastra electrode, lowering the voltage V at node 5. , as shown in Figure 1114,
A KP channel lid transistor 61 is inserted between the 1-run star 22 and the node 5. In this case, the potential of node 12 drops below the potential of node 6, turning on transistor 11, and at the time of death, node 1
In order to prevent the channel of the transistor 61 from being formed there, the potential of the transistor 61 is lowered by lowering the potential of the inverter 6 whose power source is VCC.
1if is provided, and its output is input to the transistor 61.
インバーター５の前段のインバーター６はトランジスタ
ｉｔ、ｔｉｅよシなり、信号Ｈの反転信号Ｋｌ得る。The inverter 6 in the preceding stage of the inverter 5 consists of transistors it and tie, and obtains an inverted signal Kl of the signal H.
一方、第４図においてＶ□電位がＯｖの場合、節点３ノ
はＯｖＫなりてしまう。このためトランジスタａｘ、ａ
ｓが共にオフとな〉、節点３５が７０−ティングとなる
。しかし本来は、節点３５はＯｖでトランジスタ２ｓは
オンしていなければいけなり。そのためにトランジスタ
Ｃ＃を設は鋏トランシスタロｐをオン状態とし。On the other hand, in FIG. 4, when the V□ potential is Ov, the node 3 becomes OvK. For this reason, transistor ax, a
s are both off>, the node 35 becomes 70-ting. However, originally, the node 35 should be Ov and the transistor 2s should be on. For this purpose, the transistor C# is set and the scissor transistor R is turned on.
節点３５をＯＶとしている。The node 35 is set as OV.
なお、本発明は実施例の与に＠られることなく、本発明
の要旨を逸脱しない範囲で種々の応用が可能である。例
えば第５図に示される如く、１１１２図のトランジスタ
２３ｔ／童イポーラトランジスタ１１で置き換えたり、
第６図に示される如＜ｔｌｌｌＬＺ図のトランジスタ”
ｅ １ ’Ｊ ｌ／ｆイＩ−ラトランノスタｒｘ、ｒ
ｚで置き換えてもよい。これらパイ４−ラトランジスタ
はＣＭＯＩ工程中に同時につくれるので、ＰＥＰの工程
増加とはならない。えだしこの場合ｖｃｃ或いはｖＰＰ
とパイＩ−ラトランジスタのベース間に電ｍが流れるの
で、スタンドパイ時に直流・すｔ＊らう場合には、前実
施′例で示し良ような完４＆ｃＭＯ１構成が好ましい。Note that the present invention is not limited to the embodiments, and can be applied in various ways without departing from the gist of the present invention. For example, as shown in FIG. 5, the transistor 23t in FIG.
As shown in FIG.
e 1 'J l/f i-latrannosta rx, r
It may be replaced with z. Since these piezoelectric transistors can be manufactured simultaneously during the CMOI process, no additional PEP process is required. In this case vcc or vpp
Since an electric current m flows between the base of the piezoelectric transistor and the piezoelectric transistor, a complete 4&cMO1 configuration as shown in the previous embodiment is preferable when direct current is used in a standby transistor.
１３〜１５は過大なペース電流を流さぬための抵抗であ
る。また第７Ｉｉｌｌに示される如く、第４図のＦラン
ジスタＪＪＩパイ４−ラトランジスタ１１で置き換えた
り、第８８ａに示される如く第４図のトランジスタ２２
゜２３．６１ｔ／◆イー−ラトランジスタ７２＃１１、
ＩＩＩで置自換え°Ｃもよい、ＩＩは過大なペース電流
ｔＲさぬための抵抗で弗る。また本発明はＰ−Ｗ＠ ｌ
ｌ ＩＩ ＣＭＯｓ＃ＩＩ造、？ｗ１１１−ｖ＠ｌｌ
ｌｌＣＭＯａ構造、或いはエピタキシャルＷｉｃＭｏＢ
′＃Ｉ造を周辺回路に応用できること、またセルとして
、電気的に書自換え可能なものを用いることが可能であ
る。13 to 15 are resistors for preventing excessive pace current from flowing. Also, as shown in FIG. 7Iill, the F transistor JJI piezoelectric transistor 11 of FIG. 4 may be replaced, or the transistor 22 of FIG.
゜23.61t/◆Era transistor 72#11,
It is also possible to replace III with a resistor to prevent excessive pace current tR. Further, the present invention provides P-W@l
l II CMOs #II construction? w111-v@ll
llCMOa structure or epitaxial WicMoB
'#I structure can be applied to peripheral circuits, and cells that can be electrically rewritten can be used.
発明の詳細
な説明した如く本発明によれば、電位切シ換えスイッチ
によシ１．完全ＣＭＯＢノロセスによりてメモリー回路
本体内に書き込み用高電位ｖＰ２、読み出し用電位ｖｃ
ｃ′ｔ−発生させることが可能に、などた。また従来の
ような＠ＣＭＯ８＋ ｒルッシ、：／ｍ のような豪合
ｌロセスを排除し、ｐｉｃｐの工程数を低減できる。ま
た回路設計も、ＣＭＯＩ構成であることにより回路マー
ジンを大As described in detail, according to the present invention, the potential changeover switch provides: 1. A high potential vP2 for writing and a potential VC for reading are created in the memory circuit body by complete CMOB process.
c′t-can be generated, etc. Furthermore, the conventional process such as @CMO8+Russi:/m can be eliminated, and the number of picp steps can be reduced. In addition, the circuit design has a CMOI configuration, which increases the circuit margin.
第１図は従来回路の説明図、第２図は本１発例の二１１
施例を示す回路図、嬉３図は同回路が適用されるメモリ
ー回路図、第４ｗＪないし５ｔａｙｓは本発明の他の実
施例を示す回路図である。
！・・・書き込み電位供給用節点、２・・・読み出し電
位供給用節点、５・・・電位切少換え節点、２２゜２３
．６１・・・Ｅ型トランジスタ、４Ｉｊ・・・メモリー
セルｅアレイ、１１，１１．８１・・・パイーーラトラ
ンジスタ。
出願人代理人 弁理士 鈴 江 Ｒ彦ＩＩｓ図
第６図
第８図Figure 1 is an explanatory diagram of the conventional circuit, and Figure 2 is an example of 211 of this 1st example.
Figure 3 is a circuit diagram showing an embodiment, Figure 3 is a memory circuit diagram to which the same circuit is applied, and Figures 4 to 5 are circuit diagrams showing other embodiments of the present invention. ! ...Write potential supply node, 2...Read potential supply node, 5...Potential switching node, 22゜23
．． 61...E-type transistor, 4Ij...memory cell e-array, 11,11.81...pillar transistor. Applicant's agent Patent attorney Suzue Rhiko IIs Figure 6 Figure 8
Claims (6)
と読み出し用電位が印加される０Ｍ０８回路をメモリー
七ル・アレイの周辺部に有する不揮発性メ毫り一におい
て、前記書自込み用高電位源と電位切〉換え節点との間
に第１のエンハンエンハンスメント型トランジスタを接
続し、前記Ｉｌｌのエンハンスメント製トランジスタの
サブストレート電極は前記書龜込み用高電位源側Ｋｉｌ
絖し、前記第２のエンハンスメント型トランジスタのサ
ブストレート電極は前記電位切り換え節点側Ｋｉｌ続し
、前記ＪＩ１１のエンＩ・ンスメ／）臘トランジスタは
そのダートにデータ書き込み時に導通する信号が印加さ
れ、前記ＩＩ２のエンハンスメント型トランジスタは七
のｒ−トにデータ読み出し時に導通する信号が印加され
ることを特徴とする不揮発性メモリー。(1) In a non-volatile memory system having a 0M08 circuit in the periphery of the memory array to which at least four write high potentials and read potentials are applied as an external power supply, the write high potential A first enhancement type transistor is connected between the potential source and the potential switching node, and the substrate electrode of the enhancement transistor of the Ill is connected to the high potential source side Kil for writing.
The substrate electrode of the second enhancement type transistor is connected to the potential switching node side, and a signal that becomes conductive at the time of data writing is applied to the dirt of the JI11 transistor. The enhancement type transistor II2 is a non-volatile memory characterized in that a signal that becomes conductive when reading data is applied to the seventh r-gate.
を一々イ４−ラ蓋トランジスタに置自換えた特許請求の
範囲第１項に記載の不揮発性メモリー〇(2) The non-volatile memory according to claim 1, in which each of the second enhancement type transistors is replaced with a four-layer lid transistor.
ンジスタをパイＩ−ラ型トランジスタに置自換えた特許
請求の範囲第１項に記載の不揮発性メモリー。(3) TM Book 1. 2. The nonvolatile memory according to claim 1, wherein the second enhancement type transistor is replaced with a pie-ra type transistor.
出し用電位が印加されるＣＭＯ畠回路をメモリーセル・
アレイの周辺ＷＡＫ有する不揮発性メモリーにおいて、
前記書き込み用高電位源と電位切シ換え節点との間に纂
１．第２のエン・・ンスメント型トランジスタを直列接
続し、前記読み出し用電位源と前記電位切〕換え節点と
の間に第３のエンハンスメント製トランジスタを接続し
、前記第１のエンハンスメント型トランジスタのサブス
トレート電極は前記書自込み用高電位源側に接続し、前
記８２のエン−・ンス前記ｍ１．ｍ２０エンハンスメン
ト型トランシスｌはそのｒ−）にデータ書自込与時に導
通する信号が印加され、前記第３のエンハンスメント臘
トランゾスタはそのｒ−トにデータ読み出し時に導通す
為信号が印加されることを特徴とすゐ不揮発性メモリー
。(4) The CMO Hatake circuit, to which at least a high potential for writing and a potential for reading are applied as an external power supply, is used as a memory cell.
In non-volatile memory with WAK around the array,
A wire is connected between the writing high potential source and the potential switching node. A second enhancement type transistor is connected in series, a third enhancement transistor is connected between the read potential source and the potential switching node, and a substrate of the first enhancement type transistor is connected. The electrode is connected to the writing high potential source side, and the 82 engines m1. The m20 enhancement type transistor l has a signal applied to its r-to which becomes conductive when writing data, and the third enhancement type transistor has a signal applied to its r-to which makes it conductive when reading data. Features: Non-volatile memory.
ｔＡイポーラ臘トランジスタで置き換え九特許請求の範
囲第４項に記載の不揮発性メモリー・(5) The non-volatile memory according to claim 4 is replaced with the third enhancement type transistor tApolar transistor.
皺トランゾスタｔバイポーラ臘トランジスタで置龜換え
た特許請求の範ｆｉ票４項に記載の不揮発性メ峰り−０(6) The non-volatile memory-0 described in item 4 of the patent claim, which is replaced with a bipolar transistor in the front wiring 1 to iris 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56213616A JPS58114396A (en) | 1981-12-26 | 1981-12-26 | Nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56213616A JPS58114396A (en) | 1981-12-26 | 1981-12-26 | Nonvolatile memory |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3344996A Division JPH0799635B2 (en) | 1991-12-26 | 1991-12-26 | Non-volatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58114396A true JPS58114396A (en) | 1983-07-07 |
| JPH0323999B2 JPH0323999B2 (en) | 1991-04-02 |
Family
ID=16642120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56213616A Granted JPS58114396A (en) | 1981-12-26 | 1981-12-26 | Nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58114396A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0137245A2 (en) * | 1983-08-30 | 1985-04-17 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
| JPS60180000A (en) * | 1984-02-03 | 1985-09-13 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Integrated circuit having fet transistor and programmable read only memory |
| JPS6134796A (en) * | 1984-07-25 | 1986-02-19 | Toshiba Corp | Row decoder circuit of non-volatile memory |
| JPS61186019A (en) * | 1985-02-13 | 1986-08-19 | Toshiba Corp | Logic circuit |
| EP0206710A2 (en) * | 1985-06-17 | 1986-12-30 | Advanced Micro Devices, Inc. | CMOS high voltage switch |
| JPS62124700A (en) * | 1985-11-25 | 1987-06-05 | Mitsubishi Electric Corp | Power source switching circuit |
| JPS62143297A (en) * | 1985-12-18 | 1987-06-26 | Hitachi Ltd | Semiconductor storage device |
| EP0317984A2 (en) * | 1987-11-24 | 1989-05-31 | Kabushiki Kaisha Toshiba | Nonvolatile memory |
| EP0322002A2 (en) * | 1987-12-01 | 1989-06-28 | STMicroelectronics S.r.l. | Voltage supply switching device for nonvolatile memories in MOS technology |
| FR2631503A1 (en) * | 1988-05-10 | 1989-11-17 | Thomson Video Equip | Interfacing circuit for delivering analogue clock signals to a charge transfer device |
| JPH02187997A (en) * | 1989-01-16 | 1990-07-24 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH05242690A (en) * | 1992-06-19 | 1993-09-21 | Toshiba Corp | Eeprom |
| WO2004095470A1 (en) * | 2003-04-24 | 2004-11-04 | Fujitsu Limited | Nonvolatile semiconductor memory |
| JP2008202299A (en) * | 2007-02-20 | 2008-09-04 | Oiles Eco Corp | Blind device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54124442U (en) * | 1978-02-17 | 1979-08-31 |
-
1981
- 1981-12-26 JP JP56213616A patent/JPS58114396A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54124442U (en) * | 1978-02-17 | 1979-08-31 |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0137245A2 (en) * | 1983-08-30 | 1985-04-17 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
| JPS60180000A (en) * | 1984-02-03 | 1985-09-13 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Integrated circuit having fet transistor and programmable read only memory |
| JPH0587918B2 (en) * | 1984-02-03 | 1993-12-20 | Fuiritsupusu Furuuiranpenfuaburiken Nv | |
| JPH0348596B2 (en) * | 1984-07-25 | 1991-07-24 | Tokyo Shibaura Electric Co | |
| JPS6134796A (en) * | 1984-07-25 | 1986-02-19 | Toshiba Corp | Row decoder circuit of non-volatile memory |
| JPS61186019A (en) * | 1985-02-13 | 1986-08-19 | Toshiba Corp | Logic circuit |
| JPH0519798B2 (en) * | 1985-02-13 | 1993-03-17 | Tokyo Shibaura Electric Co | |
| EP0206710A2 (en) * | 1985-06-17 | 1986-12-30 | Advanced Micro Devices, Inc. | CMOS high voltage switch |
| JPH0529997B2 (en) * | 1985-11-25 | 1993-05-06 | Mitsubishi Electric Corp | |
| JPS62124700A (en) * | 1985-11-25 | 1987-06-05 | Mitsubishi Electric Corp | Power source switching circuit |
| JPS62143297A (en) * | 1985-12-18 | 1987-06-26 | Hitachi Ltd | Semiconductor storage device |
| EP0317984A3 (en) * | 1987-11-24 | 1991-01-09 | Kabushiki Kaisha Toshiba | Nonvolatile memory |
| US5016218A (en) * | 1987-11-24 | 1991-05-14 | Kabushiki Kaisha Toshiba | Nonvolatile memory with data write circuitry to reduce write errors |
| EP0317984A2 (en) * | 1987-11-24 | 1989-05-31 | Kabushiki Kaisha Toshiba | Nonvolatile memory |
| EP0322002A2 (en) * | 1987-12-01 | 1989-06-28 | STMicroelectronics S.r.l. | Voltage supply switching device for nonvolatile memories in MOS technology |
| FR2631503A1 (en) * | 1988-05-10 | 1989-11-17 | Thomson Video Equip | Interfacing circuit for delivering analogue clock signals to a charge transfer device |
| JPH02187997A (en) * | 1989-01-16 | 1990-07-24 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH05242690A (en) * | 1992-06-19 | 1993-09-21 | Toshiba Corp | Eeprom |
| WO2004095470A1 (en) * | 2003-04-24 | 2004-11-04 | Fujitsu Limited | Nonvolatile semiconductor memory |
| US7280413B2 (en) | 2003-04-24 | 2007-10-09 | Fujitsu Limited | Nonvolatile semiconductor memory |
| JP2008202299A (en) * | 2007-02-20 | 2008-09-04 | Oiles Eco Corp | Blind device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0323999B2 (en) | 1991-04-02 |
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