JPS58111462A - Packet transmitter - Google Patents
Packet transmitterInfo
- Publication number
- JPS58111462A JPS58111462A JP56212001A JP21200181A JPS58111462A JP S58111462 A JPS58111462 A JP S58111462A JP 56212001 A JP56212001 A JP 56212001A JP 21200181 A JP21200181 A JP 21200181A JP S58111462 A JPS58111462 A JP S58111462A
- Authority
- JP
- Japan
- Prior art keywords
- packet
- pulse
- processor
- information
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は内部処理時間の測定を容易なものとすんのに好
運ならしめたパケット伝送Ｖ＆瞳に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a packet transmission V&P which facilitates and facilitates the measurement of internal processing times.
従来、この種のパケット伝送りｅＮＩ−とじて、第１図
に示すものがあった。図に於いて、１１）はプロセス入
力管ある一定長のデータにパケット化するプロセッサ、
（２１はプロセッサ（１）からのパケットヲ入力し伝送
路へ送出する通信制制欝験で、上記プロセッサ（１）、
通信＃１１！ＷＩＪ装［２）ＪＣは親時計０１）、子時
計ｔ２υを内蔵し、内部処理時間が測定されるようにな
っている。なお、イ３）は上記プロセッサ１１）及び通
偵開側装＃Ｃ２１を備えたパケット伝送装着を示す。Conventionally, there has been an eNI for this type of packet transmission as shown in FIG. In the figure, 11) is a processor that packetizes the process input pipe into data of a certain length;
(21 is a communication control system that inputs packets from the processor (1) and sends them to the transmission path; the processor (1),
Communication #11! WIJ system [2) JC has a built-in master clock 01) and a slave clock t2υ, and internal processing time is measured. Incidentally, A3) shows a packet transmission installation equipped with the processor 11) and the transmitter opening device #C21.
すなわち、第１図−成における内部処理語間の測定につ
いて以下述べると、先ずプロセッサ（１）は特定の情報
を入力した時刻を親時計ａυで求め、これを記録し、パ
ケットとともに通信制硯装晴へ出方する。そして次に、
通信制側装績（２１では、その入力時刻を子時計りηで
求めると共に上記パケットの送信完了時刻を求め、該入
力時刻と送信完了時刻とからンフト吟エアによって、処
理時間を計賞するようになっている。That is, to describe the measurement of the internally processed word in FIG. I'm leaving for the sunny day. And then,
The communication system side (21) calculates the input time using the child clock η, calculates the transmission completion time of the packet, and calculates the processing time from the input time and the transmission completion time using the input time. It has become.
処理時間を正確に出すために、例えば通信制（財）製置
（２１ヘプロセツサ（１１の邪時計ｎｔｔの時刻を通知
することによって通信制御装置（２）の子時計（ハ）を
校正し、同期をとるようになされている。In order to accurately calculate the processing time, for example, the child clock (c) of the communication control device (2) is calibrated and synchronized by notifying the time of the evil clock ntt of the communication system (21 heprocessor) (11). It is designed to take
ｔＮ来の装置は鉤止のように製放されているので、内部
処理時間を求めるのに子時計−の校正が必要で、特に短
かい処理時間を要求される伝送装置にＰいては、子時計
（ハ）の校正に要する処理時間のオバーヘット°も無視
できないものとなっていた、又。Since conventional devices are manufactured in an open-release manner, it is necessary to calibrate the slave clock in order to determine the internal processing time. The processing time overhead required to calibrate the clock (c) was also non-negligible.
最近の様に情報の入力部分をパケット化する部分と異な
るプロセッサで一寵する場合には、烙らに時計が必獅で
、またその校正が必要となり処理が煩雑になるという欠
点がある、
本発明は、上記の様な従来のものの欠点を除去するため
になされたもので、プロセス間の時計の校正を軍勢とし
、したがって無駄なオーバーヘッド時開を伝送装置から
省いて、内部処理時間を求めるのに好適ならしめるご去
ができるパケット伝送値＃を提供するものである。Recently, when the input part of the information is handled by a processor different from the part that packetizes it, there is a disadvantage that a clock is required and its calibration is required, making the processing complicated. The invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is possible to calibrate the clock between processes, eliminate unnecessary overhead time opening from the transmission device, and calculate the internal processing time. It provides a packet transmission value # that can be set to be suitable for this purpose.
Ｎ下１本発明の一実施例を第１図と同一部分は同一符号
を附して示す第２図に基いて説明すると、＠１ダにおい
て、プロセッサ（１）と通信制御装置Ｃ２１に−を入力
した時にパルスを出力するようになっており％またパル
ス出力装贅彌は通信制御装置がパケット送出完了時にパ
ルスを出方するようになっていて、これら両パルスの時
間差に基いて内部処理時間が測定ブれるようになってい
る。N21 An embodiment of the present invention will be explained based on FIG. 2, in which the same parts as in FIG. 1 are denoted by the same reference numerals. The pulse output device is designed to output a pulse when the communication control device completes sending a packet, and the internal processing time is calculated based on the time difference between these two pulses. The measurement is becoming unstable.
すなわち、第２図−成において、プロセッサ（１）は特
定の情報を入Ｔした時点で、まずパルス出力装置０３か
らパルスを出力する処理を行った後、情ａｔ処理してパ
ケットを出力することになり１次に通信ｆｌｌ１１１＠
Ｗ置（２１はパケットを入力し伝送路へパケットを送出
完了した時点で、パルス出力装置、Ａからパルスを出力
する処理ヲ行うようになっている、したがって、情報の
４１！１理時間の測定は、この２つのパルスの時間差を
１例えば、シンクロスコープ等の外部に婢続した測定器
で直接演１゛定することにより簡単に実施することがで
き、かくするにつ舞、従来のように時計をそれぞれ門跡
してグ岬セッサ開の時計を校正するといった煩緒な処理
が軍書で、内部処理時間を求めるのに好適なパケット伝
送値＃を得ることができる。That is, in FIG. 2, when the processor (1) receives specific information, it first performs processing to output a pulse from the pulse output device 03, and then processes the information and outputs a packet. 1st communication flll111@
When the W position (21 inputs a packet and completes sending the packet to the transmission line), the pulse output device A performs the process of outputting the pulse. Therefore, the measurement of the processing time of the information 41!1 can be easily carried out by directly determining the time difference between these two pulses using an externally connected measuring instrument such as a synchroscope. The complicated process of checking each clock and calibrating the clock is a military document, but it is possible to obtain the packet transmission value # suitable for determining the internal processing time.
なお、上記実施例は情報の入力からパケットの送出まで
について記しているが、バケヅト中＊＊酸においてはパ
ケットの受信からパケットの中継出力までの処理時間測
定に、又、逆にパケットの受信から情報の出力までの処
理語間測定にも利用で麹るのは勿論である。Note that the above embodiment describes the process from inputting information to sending out the packet, but in the middle of the bucket, it is possible to measure the processing time from receiving the packet to relaying the packet, or conversely from receiving the packet to sending the packet. Of course, it can also be used to measure the distance between words processed up to the output of information.
Ｎ上のように本発明によれば、欅数の処理装着に寸たが
る処理時間の測定が、＃Ｆ計の校正などの煩雛な処理を
要することなく、また！−酸自青の処理基間を短縮で真
、精密に測定できるパケット伝送装置が得られる、As mentioned above, according to the present invention, it is possible to measure the processing time required for processing the Keyaki number without the need for complicated processing such as calibration of the #F meter! - It is possible to obtain a packet transmission device that can accurately and precisely measure acid blue by shortening the processing interval.
第１５６は従来のパケット伝送装着を示すブロックＭ、
第２１！２１は本発明の一実施例によるパケット伝送装
置を示すブロック図である。
（１）：プロセッサ、 ＋２１：通信制御［１ｉ＃、
（３）：パケット伝送１ｊ＃。
ｏ２．＋２２１：パルス出力装置り
なお、Ｍ中、同一符号は固−１又は相桶部４＋を示す。
代理人 葛 野 信 −156th block M showing conventional packet transmission installation;
No. 21!21 is a block diagram showing a packet transmission device according to an embodiment of the present invention. (1): Processor, +21: Communication control [1i#,
(3): Packet transmission 1j#. o2. +221: Pulse output device Again, the same reference numerals in M indicate hard-1 or phase-well part 4+. Agent Shin Kuzuno −
Claims (1)
理を行うプロセッサと、このプロセッサからパケット伝
送された情報を入力し伝送開側手順に応じた処理を行っ
て伝送路へ送出する通信開側ｖｋｌｌｌｌを傳えたパケ
ット伝送装着において、上記プロセッサ内に特定の情報
を入力し友時点でパルスを出力するパルス出’ｎｉ！着
を内蔵すると共に、上記通信制制ｗｅ内にパケットの送
出完了した時点でパルスを出力するパルス出力装着を内
蔵させて、それら両パルス信号の時間差に基いて内部処
理時間を測定するようにしたことを特徴とするパケット
伝送ｆｃ駿。A processor that inputs process measurement information and contact information and performs packetization processing, and a communication open side vkllll that inputs information packeted from this processor, performs processing according to the transmission open side procedure, and sends it out to the transmission path. When a packet transmission device is installed, specific information is input into the processor and a pulse is output at the same time. In addition to incorporating a pulse output device in the above-mentioned communication control system to output a pulse when the transmission of a packet is completed, the internal processing time is measured based on the time difference between these two pulse signals. Packet transmission FC Shun characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56212001A JPS58111462A (en) | 1981-12-24 | 1981-12-24 | Packet transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56212001A JPS58111462A (en) | 1981-12-24 | 1981-12-24 | Packet transmitter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58111462A true JPS58111462A (en) | 1983-07-02 |
Family
ID=16615246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56212001A Pending JPS58111462A (en) | 1981-12-24 | 1981-12-24 | Packet transmitter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58111462A (en) |
-
1981
- 1981-12-24 JP JP56212001A patent/JPS58111462A/en active Pending
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