JPS58105626U - Timing pulse generation circuit using asynchronous input command signal - Google Patents
Timing pulse generation circuit using asynchronous input command signalInfo
- Publication number
- JPS58105626U JPS58105626U JP46782U JP46782U JPS58105626U JP S58105626 U JPS58105626 U JP S58105626U JP 46782 U JP46782 U JP 46782U JP 46782 U JP46782 U JP 46782U JP S58105626 U JPS58105626 U JP S58105626U
- Authority
- JP
- Japan
- Prior art keywords
- command signal
- timing pulse
- input
- command
- generation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Complex Calculations (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のタイミングパルス発生回路の回路図、第
2図は本考案によるタイミング六ルス発生回路の一実施
例を示す回路図である。
1.2・・−JKフリップフロップ、3・・・インバー
タ、4・・・アン″ド回路、511@11カウンタ、6
・・・ロジックゲート。FIG. 1 is a circuit diagram of a conventional timing pulse generation circuit, and FIG. 2 is a circuit diagram showing an embodiment of a timing pulse generation circuit according to the present invention. 1.2...-JK flip-flop, 3... Inverter, 4... AND circuit, 511@11 counter, 6
...Logic gate.
Claims (1)
等に必要なタイミングパルスを発生させる回路において
、前記コマンド信号をセットまたはリセット入力とし、
前記コマンド信号とは位相が独立した関係にあるクロッ
クにより前記コマンド入力を読込むフリップ70ツブと
、前爬フリップフロップ出力を入力とするカウンタと、
前記コマンド信号、クロック、フリップ70ツブ出力お
よびカウンタ出力を入力とするロジックゲートから構成
され、前記コマンド′信号が存在している期間中、任意
の時点で任意の幅のタイミングパルスを発生させること
を特徴とする非同期入力コマンド信号によるタイミング
パルス発生回路。In a circuit that generates timing pulses necessary for decoding and controlling commands from command signals input asynchronously, the command signal is used as a set or reset input,
a flip 70 tube that reads the command input using a clock whose phase is independent from the command signal; and a counter that receives the front flip-flop output as input;
It is composed of a logic gate that receives the command signal, a clock, a flip 70 tube output, and a counter output as inputs, and is capable of generating a timing pulse of any width at any time during the period in which the command' signal exists. A timing pulse generation circuit using an asynchronous input command signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP46782U JPS58105626U (en) | 1982-01-06 | 1982-01-06 | Timing pulse generation circuit using asynchronous input command signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP46782U JPS58105626U (en) | 1982-01-06 | 1982-01-06 | Timing pulse generation circuit using asynchronous input command signal |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58105626U true JPS58105626U (en) | 1983-07-18 |
JPH035946Y2 JPH035946Y2 (en) | 1991-02-15 |
Family
ID=30013541
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP46782U Granted JPS58105626U (en) | 1982-01-06 | 1982-01-06 | Timing pulse generation circuit using asynchronous input command signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58105626U (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4995550A (en) * | 1973-01-12 | 1974-09-10 | ||
JPS5492128U (en) * | 1977-12-13 | 1979-06-29 | ||
JPS56132630U (en) * | 1980-02-29 | 1981-10-07 |
-
1982
- 1982-01-06 JP JP46782U patent/JPS58105626U/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4995550A (en) * | 1973-01-12 | 1974-09-10 | ||
JPS5492128U (en) * | 1977-12-13 | 1979-06-29 | ||
JPS56132630U (en) * | 1980-02-29 | 1981-10-07 |
Also Published As
Publication number | Publication date |
---|---|
JPH035946Y2 (en) | 1991-02-15 |
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