JPS5797168A - Buffer nullification control system - Google Patents

Buffer nullification control system

Info

Publication number
JPS5797168A
JPS5797168A JP55172264A JP17226480A JPS5797168A JP S5797168 A JPS5797168 A JP S5797168A JP 55172264 A JP55172264 A JP 55172264A JP 17226480 A JP17226480 A JP 17226480A JP S5797168 A JPS5797168 A JP S5797168A
Authority
JP
Japan
Prior art keywords
address
comparing
buffer
read
nullification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55172264A
Other languages
English (en)
Other versions
JPS6059621B2 (ja
Inventor
Mikio Ito
Satoshi Koga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55172264A priority Critical patent/JPS6059621B2/ja
Publication of JPS5797168A publication Critical patent/JPS5797168A/ja
Publication of JPS6059621B2 publication Critical patent/JPS6059621B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP55172264A 1980-12-06 1980-12-06 バッファ無効化制御方式 Expired JPS6059621B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55172264A JPS6059621B2 (ja) 1980-12-06 1980-12-06 バッファ無効化制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55172264A JPS6059621B2 (ja) 1980-12-06 1980-12-06 バッファ無効化制御方式

Publications (2)

Publication Number Publication Date
JPS5797168A true JPS5797168A (en) 1982-06-16
JPS6059621B2 JPS6059621B2 (ja) 1985-12-26

Family

ID=15938667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55172264A Expired JPS6059621B2 (ja) 1980-12-06 1980-12-06 バッファ無効化制御方式

Country Status (1)

Country Link
JP (1) JPS6059621B2 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61141054A (ja) * 1984-12-14 1986-06-28 Nec Corp 情報処理装置
JPS61264455A (ja) * 1985-05-18 1986-11-22 Fujitsu Ltd 主記憶一致制御方式
JPH02294866A (ja) * 1989-05-10 1990-12-05 Hitachi Ltd 記憶制御方式
JPH03231365A (ja) * 1990-02-07 1991-10-15 Koufu Nippon Denki Kk 情報処理装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61141054A (ja) * 1984-12-14 1986-06-28 Nec Corp 情報処理装置
JPH0211931B2 (ja) * 1984-12-14 1990-03-16 Nippon Electric Co
JPS61264455A (ja) * 1985-05-18 1986-11-22 Fujitsu Ltd 主記憶一致制御方式
JPH0444975B2 (ja) * 1985-05-18 1992-07-23 Fujitsu Ltd
JPH02294866A (ja) * 1989-05-10 1990-12-05 Hitachi Ltd 記憶制御方式
JPH03231365A (ja) * 1990-02-07 1991-10-15 Koufu Nippon Denki Kk 情報処理装置

Also Published As

Publication number Publication date
JPS6059621B2 (ja) 1985-12-26

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