JPS5789349A - Decoder for error correction code - Google Patents

Decoder for error correction code

Info

Publication number
JPS5789349A
JPS5789349A JP16404280A JP16404280A JPS5789349A JP S5789349 A JPS5789349 A JP S5789349A JP 16404280 A JP16404280 A JP 16404280A JP 16404280 A JP16404280 A JP 16404280A JP S5789349 A JPS5789349 A JP S5789349A
Authority
JP
Japan
Prior art keywords
syndrome
error
rom
receiving
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16404280A
Other languages
Japanese (ja)
Inventor
Takakuni Kuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16404280A priority Critical patent/JPS5789349A/en
Publication of JPS5789349A publication Critical patent/JPS5789349A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To decode a code in less probability of erroneous decoding, by operating and processing a syndrome, which is calculated from a receiving code, and the intensity of a receiving field. CONSTITUTION:Data received by a receiver 2 is led to a register 3 and a syndrome calculating circuit 4. The intensity of the receiving field is measured for every one bit in parallel with date receiving and is converted to a binary bit error rate by an A/D converter 5 and an error rate correspondence ROM 6 and is stored in a shift register 7. Meanwhile, the syndrome calculated by the calculating circuit 4 gives an address to an error position correspondence ROM 8, and the product between outputs of both ROMs 7 and 8 is obtained by a multiplier 11 dn is applied to a control circuit 9. The cntrol circuit 9 detects a combination of error positions of the highest occurrence probability from combinations of error positions which generate the same syndrome, and the output of the error position correspondence ROM 8 at this time and the output of the register 3 are operated for exclusive OR to obtain corrected data.
JP16404280A 1980-11-22 1980-11-22 Decoder for error correction code Pending JPS5789349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16404280A JPS5789349A (en) 1980-11-22 1980-11-22 Decoder for error correction code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16404280A JPS5789349A (en) 1980-11-22 1980-11-22 Decoder for error correction code

Publications (1)

Publication Number Publication Date
JPS5789349A true JPS5789349A (en) 1982-06-03

Family

ID=15785693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16404280A Pending JPS5789349A (en) 1980-11-22 1980-11-22 Decoder for error correction code

Country Status (1)

Country Link
JP (1) JPS5789349A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5881356A (en) * 1981-11-10 1983-05-16 Kokusai Denshin Denwa Co Ltd <Kdd> Error control system
JPS6260320A (en) * 1985-09-10 1987-03-17 Toshiba Corp Error correction circuit
JPS63180221A (en) * 1987-01-21 1988-07-25 Nippon Telegr & Teleph Corp <Ntt> Soft decision decoding system
US5389847A (en) * 1991-06-28 1995-02-14 Fanuc Ltd. Rotor for a high speed induction type AC motor having a press fit stacked core

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5881356A (en) * 1981-11-10 1983-05-16 Kokusai Denshin Denwa Co Ltd <Kdd> Error control system
JPH0312500B2 (en) * 1981-11-10 1991-02-20 Kokusai Denshin Denwa Co Ltd
JPS6260320A (en) * 1985-09-10 1987-03-17 Toshiba Corp Error correction circuit
JPS63180221A (en) * 1987-01-21 1988-07-25 Nippon Telegr & Teleph Corp <Ntt> Soft decision decoding system
US5389847A (en) * 1991-06-28 1995-02-14 Fanuc Ltd. Rotor for a high speed induction type AC motor having a press fit stacked core

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