JPS578852A - Sequenced instruction execution control system - Google Patents

Sequenced instruction execution control system

Info

Publication number
JPS578852A
JPS578852A JP8329480A JP8329480A JPS578852A JP S578852 A JPS578852 A JP S578852A JP 8329480 A JP8329480 A JP 8329480A JP 8329480 A JP8329480 A JP 8329480A JP S578852 A JPS578852 A JP S578852A
Authority
JP
Japan
Prior art keywords
instructions
register
instruction
address
processing part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8329480A
Other languages
Japanese (ja)
Other versions
JPS6047615B2 (en
Inventor
Yoshihiro Mizushima
Kazuyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8329480A priority Critical patent/JPS6047615B2/en
Publication of JPS578852A publication Critical patent/JPS578852A/en
Publication of JPS6047615B2 publication Critical patent/JPS6047615B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To shorten the required time of control which corresponds to sequential instructions, by determining substantially an address for fetching a new instruction at the point in time when the sequential instructions are executed and the execution is completed. CONSTITUTION:Instructions, when read out from a storage device, are set in instruction buffer register 7-1-7-3 in sequence. On the other hand, instructions are supplied from the register 7-1 to a processing part 9 via a selector circuit 8 as the processing of a pipeline processing part 9 progrsses. For example, if instructions at positions I0-I4 in the figure are supplied to the processing part 9 and the execution is finished, only the next sequence instruction pointer NSiP5 has a logic 1. When instructions are prefetched, a register 7-3 is empty and if the pointer NSiP5 indicates a logic 1, pseudo-sequential instructions still remain in the register 7-2, determining a value for correcting the contents of an instruction address register. Consequently, the required address is determined and set in an effective address register.
JP8329480A 1980-06-19 1980-06-19 Serialized instruction execution control method Expired JPS6047615B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8329480A JPS6047615B2 (en) 1980-06-19 1980-06-19 Serialized instruction execution control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8329480A JPS6047615B2 (en) 1980-06-19 1980-06-19 Serialized instruction execution control method

Publications (2)

Publication Number Publication Date
JPS578852A true JPS578852A (en) 1982-01-18
JPS6047615B2 JPS6047615B2 (en) 1985-10-22

Family

ID=13798369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8329480A Expired JPS6047615B2 (en) 1980-06-19 1980-06-19 Serialized instruction execution control method

Country Status (1)

Country Link
JP (1) JPS6047615B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841999A (en) * 1996-04-17 1998-11-24 International Business Machines Corporation Information handling system having a register remap structure using a content addressable table
US6754814B1 (en) 1998-12-17 2004-06-22 Fujitsu Limited Instruction processing apparatus using a microprogram that implements a re-reading operation by controlling early loading of instructions

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841999A (en) * 1996-04-17 1998-11-24 International Business Machines Corporation Information handling system having a register remap structure using a content addressable table
US6754814B1 (en) 1998-12-17 2004-06-22 Fujitsu Limited Instruction processing apparatus using a microprogram that implements a re-reading operation by controlling early loading of instructions

Also Published As

Publication number Publication date
JPS6047615B2 (en) 1985-10-22

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