JPS578849A - Adjusting system for instruction execution speed - Google Patents

Adjusting system for instruction execution speed

Info

Publication number
JPS578849A
JPS578849A JP8238580A JP8238580A JPS578849A JP S578849 A JPS578849 A JP S578849A JP 8238580 A JP8238580 A JP 8238580A JP 8238580 A JP8238580 A JP 8238580A JP S578849 A JPS578849 A JP S578849A
Authority
JP
Japan
Prior art keywords
instruction
circuit
instruction execution
signal
differing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8238580A
Other languages
Japanese (ja)
Inventor
Fumio Hoshi
Masao Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8238580A priority Critical patent/JPS578849A/en
Publication of JPS578849A publication Critical patent/JPS578849A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To constitute various data processors, differing in processing performance, with ease by providing an instruction speed adjusting circuit which controls the sending point in time of a next instruction execution request signal variably, and by varying an instruction execution speed. CONSTITUTION:Between an arithmetic control circuit 5 and an instruction executing circuit 1, an instruction speed adjusting circuit 6 is provided. This circuit 6, when an instruction execution end timing signal is sent from the circuit 5, delay this signal by a preset time and then sends it as an instruction execution request timing signal to the instruction executing circuit. The functions of the said circuit 6 permits an idle time to be inserted between one instruction and the following instruction. This idle time is controlled variably to constitute various data processors differing in processing performance.
JP8238580A 1980-06-18 1980-06-18 Adjusting system for instruction execution speed Pending JPS578849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8238580A JPS578849A (en) 1980-06-18 1980-06-18 Adjusting system for instruction execution speed

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8238580A JPS578849A (en) 1980-06-18 1980-06-18 Adjusting system for instruction execution speed

Publications (1)

Publication Number Publication Date
JPS578849A true JPS578849A (en) 1982-01-18

Family

ID=13773108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8238580A Pending JPS578849A (en) 1980-06-18 1980-06-18 Adjusting system for instruction execution speed

Country Status (1)

Country Link
JP (1) JPS578849A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5983233A (en) * 1982-09-30 1984-05-14 ウエスターン　エレクトリック　カムパニー，インコーポレーテッド Variable cycle time microcomputer
EP0167853A2 (en) * 1984-06-27 1986-01-15 Compaq Computer Corporation Personal computer having normal and high speed execution modes
JPS61175732A (en) * 1985-01-30 1986-08-07 Hitachi Ltd Performance control system for information processor
JPS63163658A (en) * 1986-12-26 1988-07-07 Hitachi Ltd Information processor
JPH02178837A (en) * 1988-12-29 1990-07-11 Koufu Nippon Denki Kk Speed governing system for microprogram

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5983233A (en) * 1982-09-30 1984-05-14 ウエスターン　エレクトリック　カムパニー，インコーポレーテッド Variable cycle time microcomputer
EP0167853A2 (en) * 1984-06-27 1986-01-15 Compaq Computer Corporation Personal computer having normal and high speed execution modes
EP0167853A3 (en) * 1984-06-27 1987-02-25 Compaq Computer Corporation Personal computer having normal and high speed execution modes
JPS61175732A (en) * 1985-01-30 1986-08-07 Hitachi Ltd Performance control system for information processor
JPS63163658A (en) * 1986-12-26 1988-07-07 Hitachi Ltd Information processor
JPH02178837A (en) * 1988-12-29 1990-07-11 Koufu Nippon Denki Kk Speed governing system for microprogram

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