JPS5787642A - Binary code trnsmitting system - Google Patents

Binary code trnsmitting system

Info

Publication number
JPS5787642A
JPS5787642A JP55164354A JP16435480A JPS5787642A JP S5787642 A JPS5787642 A JP S5787642A JP 55164354 A JP55164354 A JP 55164354A JP 16435480 A JP16435480 A JP 16435480A JP S5787642 A JPS5787642 A JP S5787642A
Authority
JP
Japan
Prior art keywords
terminal
modulation
channel
demodulation
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55164354A
Other languages
Japanese (ja)
Inventor
Tsunehisa Sukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP55164354A priority Critical patent/JPS5787642A/en
Publication of JPS5787642A publication Critical patent/JPS5787642A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To increase the accuracy of equalization without interfering the automatic phase control characteristics, by obtaining a plurality of channels through frequency division of transmission frequency band of one line and making automatic equalization easy. CONSTITUTION:In a transmission system performing clock synchronization between modulation and demodulation with a channel itself between terminals 1, 2, circuits C1, C2 allocating and coupling bit signals to a frequency multiplex channel between the terminals and the terminal information source, signal processors CH1-CHN having modulation/demodulation function of each frequency multiplex channel at the terminal 1 and a clock signal source OSC are provided. Similarly, signal processors CH'1-CH'N are modulation and demodulation functions at the terminal 2. In making phase synchronization of master lock to the modulation element clock of the channel 1 of the terminal 1 at the terminal, a voltage controlled oscillator VCD is controlled with the output of the CH'1 modulator (not shown) at the terminal 2. As to the modulation element clock of other channels than CH1 CH'1, they are synchronized with the CH1 CH'1. Delay control is made at the modulation/demodulation side for the synchronism of the modulation element clock between the MODEMs of each channel.
JP55164354A 1980-11-21 1980-11-21 Binary code trnsmitting system Pending JPS5787642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55164354A JPS5787642A (en) 1980-11-21 1980-11-21 Binary code trnsmitting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55164354A JPS5787642A (en) 1980-11-21 1980-11-21 Binary code trnsmitting system

Publications (1)

Publication Number Publication Date
JPS5787642A true JPS5787642A (en) 1982-06-01

Family

ID=15791551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55164354A Pending JPS5787642A (en) 1980-11-21 1980-11-21 Binary code trnsmitting system

Country Status (1)

Country Link
JP (1) JPS5787642A (en)

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