JPS5784645A - By-pass circuit - Google Patents

By-pass circuit

Info

Publication number
JPS5784645A
JPS5784645A JP55161744A JP16174480A JPS5784645A JP S5784645 A JPS5784645 A JP S5784645A JP 55161744 A JP55161744 A JP 55161744A JP 16174480 A JP16174480 A JP 16174480A JP S5784645 A JPS5784645 A JP S5784645A
Authority
JP
Japan
Prior art keywords
signal
synchronism
communication controller
circuit
reception signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55161744A
Other languages
Japanese (ja)
Other versions
JPS6367377B2 (en
Inventor
Naruhiro Hayashi
Osamu Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55161744A priority Critical patent/JPS5784645A/en
Publication of JPS5784645A publication Critical patent/JPS5784645A/en
Publication of JPS6367377B2 publication Critical patent/JPS6367377B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Small-Scale Networks (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To suppress the effet and extension to a communication controller and terminator on and after the next stage, by by-passing the communication controller when the out of synchronism of frame of a reception signal is caused. CONSTITUTION:A signal 9 which is normally selected at a selection circuit 15 in a transmission section 4 and processed at a data processor 6 is transmitted. When the out of synchronism of the reception signal is detected at a synchronizing circuit 5, the selection circuit 15 is controlled with an out-of-synchronism signal 10, its forming signal 16, and a selecting circuit control signal 8 to transmit a reception signal 7 transmitted via a delay circuit 3. Thus, if the out of synchronism is caused in the communication controller, the communication controller is by-passed for transmission.
JP55161744A 1980-11-17 1980-11-17 By-pass circuit Granted JPS5784645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55161744A JPS5784645A (en) 1980-11-17 1980-11-17 By-pass circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55161744A JPS5784645A (en) 1980-11-17 1980-11-17 By-pass circuit

Publications (2)

Publication Number Publication Date
JPS5784645A true JPS5784645A (en) 1982-05-27
JPS6367377B2 JPS6367377B2 (en) 1988-12-26

Family

ID=15741054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55161744A Granted JPS5784645A (en) 1980-11-17 1980-11-17 By-pass circuit

Country Status (1)

Country Link
JP (1) JPS5784645A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172864A (en) * 1983-02-07 1984-09-29 エヌ・ベー・フイリップス・フルーイランペンファブリケン Time division multiplex loop electric communication system
JPS60232738A (en) * 1984-05-04 1985-11-19 Iwatsu Electric Co Ltd Loop type transmission system
JPS61255142A (en) * 1985-05-08 1986-11-12 Nec Corp Bit addition device
JPS6462929A (en) * 1987-09-02 1989-03-09 Nec Corp Repeater
JPH02143737A (en) * 1988-11-25 1990-06-01 Nec Corp Digital radio repeater
JPH0433438A (en) * 1990-05-30 1992-02-04 Fujitsu Ltd Transmission line changeover system for local area network

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940640A (en) * 1972-08-24 1974-04-16
JPS5231629A (en) * 1975-06-20 1977-03-10 Fuji Electric Co Ltd Data communiction system
JPS5336118A (en) * 1976-09-16 1978-04-04 Fujitsu Ltd Loop transmission system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940640A (en) * 1972-08-24 1974-04-16
JPS5231629A (en) * 1975-06-20 1977-03-10 Fuji Electric Co Ltd Data communiction system
JPS5336118A (en) * 1976-09-16 1978-04-04 Fujitsu Ltd Loop transmission system

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172864A (en) * 1983-02-07 1984-09-29 エヌ・ベー・フイリップス・フルーイランペンファブリケン Time division multiplex loop electric communication system
JPS60232738A (en) * 1984-05-04 1985-11-19 Iwatsu Electric Co Ltd Loop type transmission system
JPS61255142A (en) * 1985-05-08 1986-11-12 Nec Corp Bit addition device
JPH0548977B2 (en) * 1985-05-08 1993-07-23 Nippon Electric Co
JPS6462929A (en) * 1987-09-02 1989-03-09 Nec Corp Repeater
JPH02143737A (en) * 1988-11-25 1990-06-01 Nec Corp Digital radio repeater
JPH0433438A (en) * 1990-05-30 1992-02-04 Fujitsu Ltd Transmission line changeover system for local area network

Also Published As

Publication number Publication date
JPS6367377B2 (en) 1988-12-26

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