JPS5783948A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS5783948A
JPS5783948A JP55159535A JP15953580A JPS5783948A JP S5783948 A JPS5783948 A JP S5783948A JP 55159535 A JP55159535 A JP 55159535A JP 15953580 A JP15953580 A JP 15953580A JP S5783948 A JPS5783948 A JP S5783948A
Authority
JP
Japan
Prior art keywords
processor
monitoring processor
data
input
diagnosis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55159535A
Other languages
Japanese (ja)
Other versions
JPS6342989B2 (en
Inventor
Seiichi Yasumoto
Toshiyuki Ide
Hitoshi Fushimi
Masakazu Okada
Sadao Mizokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55159535A priority Critical patent/JPS5783948A/en
Publication of JPS5783948A publication Critical patent/JPS5783948A/en
Publication of JPS6342989B2 publication Critical patent/JPS6342989B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Small-Scale Networks (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To detect a device fault in its early stage and to isolate a fault position by sectioning an information processing system by hierarchies and by checking the function of each hierarchy. CONSTITUTION:In an information transfer system extending from a highest-priority main storage device 2 to a lowest-priority input-output equipment 10, a part including halfway repeaters (5, 8 and 9) is divided into hierachies as minimum sections, and the functions of each section are checked. First, when the functions of the hierachy 30 of a monitoring processor 3 and an input-output control processor 5 are checked, the monitoring processor 3 sends a start command I, which indicates the details of a diagnosis, a transfer parameter of known data, etc., to the input-output control processor 5. On receiving the start command I, this processor 5 decodes the parameter to receive written data for the diagnosis in the data area of the monitoring processor 3 by DMA transfer, and then returns the said written data to the monitoring processor 3 as readout data. After the said operation ends, the monitoring processor is informed of that and the next hierarchy check is started.
JP55159535A 1980-11-14 1980-11-14 Information processing system Granted JPS5783948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55159535A JPS5783948A (en) 1980-11-14 1980-11-14 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55159535A JPS5783948A (en) 1980-11-14 1980-11-14 Information processing system

Publications (2)

Publication Number Publication Date
JPS5783948A true JPS5783948A (en) 1982-05-26
JPS6342989B2 JPS6342989B2 (en) 1988-08-26

Family

ID=15695887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55159535A Granted JPS5783948A (en) 1980-11-14 1980-11-14 Information processing system

Country Status (1)

Country Link
JP (1) JPS5783948A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008544389A (en) * 2005-06-21 2008-12-04 エヌエックスピー ビー ヴィ Parallel testing method of data integrity of PCI Express device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5227966A (en) * 1975-08-28 1977-03-02 Akebono Brake Ind Co Ltd Tilting type disk brake

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5227966A (en) * 1975-08-28 1977-03-02 Akebono Brake Ind Co Ltd Tilting type disk brake

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008544389A (en) * 2005-06-21 2008-12-04 エヌエックスピー ビー ヴィ Parallel testing method of data integrity of PCI Express device
US8117525B2 (en) 2005-06-21 2012-02-14 Nxp B.V. Method for parallel data integrity checking of PCI express devices

Also Published As

Publication number Publication date
JPS6342989B2 (en) 1988-08-26

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