JPS5783850A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS5783850A
JPS5783850A JP55159333A JP15933380A JPS5783850A JP S5783850 A JPS5783850 A JP S5783850A JP 55159333 A JP55159333 A JP 55159333A JP 15933380 A JP15933380 A JP 15933380A JP S5783850 A JPS5783850 A JP S5783850A
Authority
JP
Japan
Prior art keywords
branch
instruction
register
address
valid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55159333A
Other languages
Japanese (ja)
Other versions
JPS6161413B2 (en
Inventor
Hisazumi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55159333A priority Critical patent/JPS5783850A/en
Publication of JPS5783850A publication Critical patent/JPS5783850A/en
Publication of JPS6161413B2 publication Critical patent/JPS6161413B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To improve the flexibility of the control, by setting preliminarily optionally whether branching between respective areas is valid or not in case that a privileged level is provided in different areas in a main storage. CONSTITUTION:An instruction 6 is read out by the address of an instruction address register 1; and if contents of a buffer register 7 are a branch instruction, addresses of the instruction address register 1 and a branch address part 9 are compared with each other. In this case, only upper N-number bits of the register 1 and the branch address part 9 are compared. If they coincide with each other, a branch in the same area is discriminated to execute the branch instruction of the buffer register 7. Otherwise, a branch to a different area is discriminated, and an entry for a branch destination area is read out from a branch control table 12 and is sent to a read branch validity check part 14. If this branch is valid, the branch instruction of the register 7 is executed; and if it is not valid, the execution of the instruction is suppressed.
JP55159333A 1980-11-12 1980-11-12 Data processing device Granted JPS5783850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55159333A JPS5783850A (en) 1980-11-12 1980-11-12 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55159333A JPS5783850A (en) 1980-11-12 1980-11-12 Data processing device

Publications (2)

Publication Number Publication Date
JPS5783850A true JPS5783850A (en) 1982-05-25
JPS6161413B2 JPS6161413B2 (en) 1986-12-25

Family

ID=15691524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55159333A Granted JPS5783850A (en) 1980-11-12 1980-11-12 Data processing device

Country Status (1)

Country Link
JP (1) JPS5783850A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0383268A2 (en) * 1989-02-13 1990-08-22 Hitachi, Ltd. Data processor in which branching during program execution is controlled by the contents of a branch address table
US6101586A (en) * 1997-02-14 2000-08-08 Nec Corporation Memory access control circuit
JP2004005679A (en) * 2002-05-29 2004-01-08 Samsung Electronics Co Ltd Computer system, memory structure, and method of executing program
GB2448149A (en) * 2007-04-03 2008-10-08 Advanced Risc Mach Ltd Protected function calling across domains
US7966466B2 (en) 2007-04-03 2011-06-21 Arm Limited Memory domain based security control with data processing systems
US9305183B2 (en) 2000-06-30 2016-04-05 Intel Corporation Method and apparatus for secure execution using a secure memory partition

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5323244A (en) * 1976-08-16 1978-03-03 Hitachi Ltd Information processing unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5323244A (en) * 1976-08-16 1978-03-03 Hitachi Ltd Information processing unit

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0383268A2 (en) * 1989-02-13 1990-08-22 Hitachi, Ltd. Data processor in which branching during program execution is controlled by the contents of a branch address table
EP0383268A3 (en) * 1989-02-13 1992-08-26 Hitachi, Ltd. Data processor in which branching during program execution is controlled by the contents of a branch address table
US6101586A (en) * 1997-02-14 2000-08-08 Nec Corporation Memory access control circuit
US9547779B2 (en) 2000-06-30 2017-01-17 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9305183B2 (en) 2000-06-30 2016-04-05 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9323954B2 (en) 2000-06-30 2016-04-26 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9507963B2 (en) 2000-06-30 2016-11-29 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9507962B2 (en) 2000-06-30 2016-11-29 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9619672B2 (en) 2000-06-30 2017-04-11 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9971909B2 (en) 2000-06-30 2018-05-15 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US10572689B2 (en) 2000-06-30 2020-02-25 Intel Corporation Method and apparatus for secure execution using a secure memory partition
JP2004005679A (en) * 2002-05-29 2004-01-08 Samsung Electronics Co Ltd Computer system, memory structure, and method of executing program
GB2448149A (en) * 2007-04-03 2008-10-08 Advanced Risc Mach Ltd Protected function calling across domains
GB2448149B (en) * 2007-04-03 2011-05-18 Advanced Risc Mach Ltd Protected function calling
US7966466B2 (en) 2007-04-03 2011-06-21 Arm Limited Memory domain based security control with data processing systems
US8010772B2 (en) 2007-04-03 2011-08-30 Arm Limited Protected function calling

Also Published As

Publication number Publication date
JPS6161413B2 (en) 1986-12-25

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