JPS57740A - Key input processing system - Google Patents

Key input processing system

Info

Publication number
JPS57740A
JPS57740A JP7514680A JP7514680A JPS57740A JP S57740 A JPS57740 A JP S57740A JP 7514680 A JP7514680 A JP 7514680A JP 7514680 A JP7514680 A JP 7514680A JP S57740 A JPS57740 A JP S57740A
Authority
JP
Japan
Prior art keywords
signals
buffer
arithmetic
keys
ram23
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7514680A
Other languages
Japanese (ja)
Inventor
Toshifusa Iwamaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP7514680A priority Critical patent/JPS57740A/en
Publication of JPS57740A publication Critical patent/JPS57740A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Clocks (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To eliminate the need for a special circuit for chattering removal by inputting key output signals in time-division mode under microprogram control and by performing arithmetic processing.
CONSTITUTION: In an electronic wrist watch with a computing function, a counter 26 in an RAM23 is accessed by a microprogram (μPG) instruction in an ROM21 and counting operation is repeated for every digit. The contents of the counter 26 are read in a buffer 27 successively and according to the cotents, "1" signals are outputted successively from output lines l1Wl5 of a decoder 28. When ten keys 13 are operated, sampling signals are outputted from output lines of a key matrix circuit 30 and read in a buffer 31. With the timing of signals from lines l0Wl3, data is sent from the buffer 31 to an arithmetic part 24 through a gate circuit 29 and a transfer gate 32. From the arithmetic part 24 to the RAM23, key input data is written and chattering removing processing is carried out through software. With arithmetic specifying keys 14aW14d and mode specifying keys 15aW15d, the same processing is performed.
COPYRIGHT: (C)1982,JPO&Japio
JP7514680A 1980-06-04 1980-06-04 Key input processing system Pending JPS57740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7514680A JPS57740A (en) 1980-06-04 1980-06-04 Key input processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7514680A JPS57740A (en) 1980-06-04 1980-06-04 Key input processing system

Publications (1)

Publication Number Publication Date
JPS57740A true JPS57740A (en) 1982-01-05

Family

ID=13567762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7514680A Pending JPS57740A (en) 1980-06-04 1980-06-04 Key input processing system

Country Status (1)

Country Link
JP (1) JPS57740A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154527A (en) * 1983-02-22 1984-09-03 Tokyo Electric Co Ltd Electronic typewriter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154527A (en) * 1983-02-22 1984-09-03 Tokyo Electric Co Ltd Electronic typewriter
JPH04292B2 (en) * 1983-02-22 1992-01-07 Tokyo Electric Co Ltd

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