JPS5769418A - Runaway detector - Google Patents

Runaway detector

Info

Publication number
JPS5769418A
JPS5769418A JP55145784A JP14578480A JPS5769418A JP S5769418 A JPS5769418 A JP S5769418A JP 55145784 A JP55145784 A JP 55145784A JP 14578480 A JP14578480 A JP 14578480A JP S5769418 A JPS5769418 A JP S5769418A
Authority
JP
Japan
Prior art keywords
signal
level
latch
runaway
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55145784A
Other languages
Japanese (ja)
Inventor
Naohiro Kurokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55145784A priority Critical patent/JPS5769418A/en
Publication of JPS5769418A publication Critical patent/JPS5769418A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Testing And Monitoring For Control Systems (AREA)

Abstract

PURPOSE:To constitute a detector at low cost only with hardware without spoiling reliability, by inhibiting the functions of a runaway detection part a prescribed period after the power source of a microcomputer-applied system is put to work. CONSTITUTION:With a reset switch 94 pushed, a signal from a gate 96 in a resetting circuit 9 is inputted to the terminal RES of a CPU2 and a signal having a level 1 generated on an address line A14 for runaway detection is applied to the terminal CLK of a latch 100, but a latch control signal having a level 0 is applied to the terminal CLK for a prescribed period, inhibiting a latching function. In case of a runaway, an address signal 1 is generated on the address line A14 and a signal having a level 1 is applied to the terminal CLK of the latch 100. Then, the latch 100 output a level 1 (Vcc) applied to the terminal D to drive a load 8' for emergency processing, thereby turning on, for example, a runaway indicating lamp which is not shown in the figure.
JP55145784A 1980-10-20 1980-10-20 Runaway detector Pending JPS5769418A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55145784A JPS5769418A (en) 1980-10-20 1980-10-20 Runaway detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55145784A JPS5769418A (en) 1980-10-20 1980-10-20 Runaway detector

Publications (1)

Publication Number Publication Date
JPS5769418A true JPS5769418A (en) 1982-04-28

Family

ID=15393076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55145784A Pending JPS5769418A (en) 1980-10-20 1980-10-20 Runaway detector

Country Status (1)

Country Link
JP (1) JPS5769418A (en)

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